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[AK4950] ms1320-e-00 2011/10 - 1 - general description the AK4950 is a 24bit stereo codec with a mi crophone, speaker and headphone am plifiers. the input circuits include a microphone amplifier and the output circuits in clude a speaker amplifier. it is suitable for portable application with recordi ng/playback function. the integrat ed charge pump generates an internal negative power supply rail and removes the output c oupling capacitor. a one c hannel composite in/out video amplifier is also integrated. digital sound processing is provided by the internal dsp. the AK4950 is available in a small 32pin qfn (4mm x 4mm, 0.4mm pitch), saving more board space. features 1. recording functions ? stereo single-ended input with two selectors ? mic amplifier (+24db/+21db/+18db/ +16db/+14db/+11db/+8db/+5db/0db) ? digital alc (automatic level control) (setting range: +35.625db ? 54db, 0.375db step) ? adc performance: s/(n+d): 83db, dr, s/n: 88db (mic-amp=+18db) s/(n+d): 85db, dr, s/n: 96db (mic-amp=0db) ? mic sensitivity compensation ? wind-noise reduction filter ? 4 band notch filter ? stereo separation emphasis circuit ? digital mic interface 2. playback functions ? digital de-emphasis filter (tc=50/15 s, fs=32khz, 44.1khz, 48khz) ? digital alc (automatic level control) (setting range: +35.625db ~ ? 54db, 0.375db step) ? digital volume control (+12db ~ ? 78db, 0.375db step) ? stereo separation emphasis circuit ? stereo line output - s/(n+d): 83db, s/n: 92db ? mono mixing output ? mono speaker-amplifier - spk-amp performance: s/(n +d): 75db@150mw, 70db@250mw, s/n: 95db - thermal shut-down - btl output - output power: 400mw@8 (svdd=3.3v) ? analog mixing: mono input 3. power management 4. master clock: (1) pll mode ? frequencies: 11.2896mhz, 12mhz, 13.5m hz, 24mhz, 25mhz, 27mhz (mcki pin) 32fs or 64fs (bick pin) (2) external clock mode ? frequencies: 512fs or 1024fs (mcki pin) AK4950 24bit stereo codec with mic/spk/ca p -less video-amp & mini dsp
[AK4950] ms1320-e-00 2011/10 - 2 - 5. output master clock fr equencies: 32fs/64fs/128fs/256fs ? pll slave mode (bick pin): 7.35khz 48khz ? pll slave mode (mcki pin): 8khz, 11.025khz, 12khz, 16khz, 22.05kh z, 24khz, 32khz, 44.1khz, 48khz ? pll master mode: 8khz, 11.025khz, 12khz, 16khz, 22.05kh z, 24khz, 32khz, 44.1khz, 48khz ? ext master/slave mode: 7.35khz 48khz (512fs), 7.35khz 13khz (1024fs) 6. p i/f: 3-wire mode, i 2 c bus (ver 1.0, 400khz fast-mode) 7. master/slave mode 8. audio interface format: msb first, 2?s complement ? adc: 24bit msb justified, 16/24bit i 2 s ? dac: 24bit msb justified, 16bit lsb justified, 24bit lsb justified, 16/24bit i 2 s 9. video functions ? one composite signal input ? capacitor-less video amplifier for composite signal output gain: +6 / +9 / +12 / +16.5db ? lpf ? charge pump circuit for negative power supply 10. ta = ? 30 85 c 11. power supply: ? analog power supply (avdd): 2.7 ~ 3.6v ? digital i/o power supply (tvdd): 1.6 ~ 3.6v 12. package: 32pin qfn (4 x 4mm, 0.4mm pitch)
[AK4950] ms1320-e-00 2011/10 - 3 - block diagram regfila tvdd bick lrck sdto sdti vss2 pmpfil pll pmpll mcko mcki vout pmv composite video out +6/9/12/16.5db lpf vin pmdac speaker spp spn pmspk spk-amp control register cclk/scl cdtio/cad0 csn/sda i2c mic power supply mic-amp a/d hpf pmadl pmadr pmmp pmadl or pmadr internal mic external mic mpwr lin1 rin1 lin2 rin2 avdd charge pump line out lout vss4 pvee pdn vcom audio i/f vss1 ldo: 2.3v ldo: 1.8v analog block digital block mic power, spk-amp, line/video-out-amp vss3 regfilb clamp clk gen pmcp 3 band eq alc lpf hpf2 stereo separation 1 band eq d/a dem mono/ stereo dvol smute rout/min pmbp pmlo mic sensitivity com p ensation figure 1. block diagram total: 32pin
[AK4950] ms1320-e-00 2011/10 - 4 - ordering guide AK4950en 30 a +85 q c 32pin qfn (0.4mm pitch) akd4950 evaluation board for AK4950 pin layout vss3 avdd vcom vss1 vout vss4 pvee vin spn spp i2c regfila regfilb mcko mcki vss2 rout/min lout lin1 rin1 mpw r lin2 rin2 pdn tvdd bick lrck sdto sdti cdtio/cad0 cclk/scl csn/sda AK4950en top view 25 26 27 28 29 30 31 32 24 23 22 1 16 15 14 13 12 11 10 9 21 20 19 2 3 4 5 6 7 8 18 17
[AK4950] ms1320-e-00 2011/10 - 5 - pin/function no pin name i/o function rout o rch analog output pin (pmbp bit = ?0?) 1 min i mono analog signal input pin (pmbp bit = ?1?) 2 lout o lch analog output pin lin1 i lch analog input line input 1pin (dmic bit = ?0?) 3 dmdat i digital microphone data input pin (dmic bit = ?1?) rin1 i rch analog input 1 pin (dmic bit = ?0?) 4 dmclk o digital microphone clock pin (dmic bit = ?1?) 5 mpwr o mic power supply pin for microphone 6 lin2 i lch analog input 2 pin 7 rin2 i rch analog input 2 pin 8 pdn i power-down & reset when ?l?, the AK4950 is in power-down mode and is held in reset. the AK4950 must be always reset upon power-up. csn i chip select pin (i2c pin = ?l?) 9 sda i/o control data input/output pin (i2c pin = ?h?) cclk i control data clock pin (i2c pin = ?l?) 10 scl i control data clock pin (i2c pin = ?h?) cdtio i/o control data input/output pin (i2c pin = ?l?) 11 cad0 i chip address select pin (i2c pin = ?h?) 12 sdti i audio serial data input pin 13 sdto o audio serial data output pin 14 lrck i/o input/output channel clock pin 15 bick i/o audio serial data clock pin 16 tvdd - digital i/f power supply pin 17 vss2 - ground 2 pin 18 mcki i external master clock input pin 19 mcko o master clock output pin 20 regfilb o ldo voltage output pin for digital logic (typ 1.8v) this pin must be connected to the vss1 pin with a 1.0 f capacitor (50% including tolerance and temperat ure allowance) in series. 21 regfila o ldo voltage output pin for analog logic (typ 2.3v) this pin must be connected to the vss1 pin with a 2.2 f capacitor (50% including tolerance and temperat ure allowance) in series. 22 i2c i control mode select pin ?h?: i 2 c bus, ?l?: 3-wire mode the input circuit of the i2c pin is operated by avdd. 23 spp o speaker amp positive output pin 24 spn o speaker amp negative output pin 25 vss3 - ground 3 pin 26 avdd - analog power supply pin this pin must be connected to vss4 with a 0.1 f ceramic capacitor in series. 27 vcom o common voltage output pin bias voltage of adc inputs and dac outputs. 28 vss1 - ground 1 pin 29 vout o composite video output pin 30 vss4 - ground 4 pin 31 pvee o negative voltage output pin for video output this pin must be connected to vss4 with a 2.2 f ceramic capacitor in series. 32 vin i composite video input pin note 1. all input pins except analog input pins (min, lin1, rin1, lin2, rin2, vin) must not be allowed to float.
[AK4950] ms1320-e-00 2011/10 - 6 - handling of unused pin unused i/o pins must be processed appropriately as below. classification pin name setting analog mpwr, spn, spp, rout/min, lout, rin2, lin2, lin1/dmdat, rin1/dmclk, vin, vout these pins must be open. mcko this pin must be open. digital mcki this pin must be connected to vss2. absolute maximum ratings (vss1=vss2=vss3=vss4=0v; note 2 ) parameter symbol min max unit power supplies: analog avdd 0.3 6.0 v digital i/o tvdd 0.3 6.0 v input current, any pin except supplies iin - r 10 ma analog input voltage ( note 4 ) vina 0.3 avdd+0.3 v digital input voltage ( note 5 ) vind 0.3 tvdd+0.3 v ambient temperature (powered applied) ta 30 85 q c storage temperature tstg 65 150 q c maximum power dissipation ( note 6 ) pd1 - 450 mw note 2. all voltages are with respect to ground. note 3. vss1, vss2, vss3 and vss4 must be connected to the same analog ground plane. note 4. min, lin1, rin1, lin2, rin2, vin, i2c pins note 5. pdn, csn, cclk, cdtio, sdti, lrck, bick, mcki pins note 6. in case that pcb wiring dens ity is over 200% and its surface wiring de nsity is over 50%. this power is the AK4950 internal dissipation that does not include power dissipation of externally connected speakers. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guara nteed at these extremes. recommended operating conditions (vss1=vss2=vss3=vss4=0v; note 2 ) parameter symbol min typ max unit power supplies analog avdd 2.7 3.3 3.6 v ( note 7 ) digital i/o tvdd 1.6 1.8 3.6 v note 2. all voltages are with respect to ground. note 7. the power-up sequence between avdd and tvdd is not critical. the pdn pin must be ?l? upon power up, and should be changed to ?h? after all power supplies are supplied to avoid an internal circuit error. * when tvdd is powered on and the pdn pin is ?l?, avdd can be powered on/off. when the AK4950 is powered on from power-down state, the pdn pin must be ?h? after all power supplies are on. * akm assumes no responsibility for the usage beyond the conditions in this datasheet.
[AK4950] ms1320-e-00 2011/10 - 7 - analog characteristics (ta=25 c; avdd=3.3v, tvdd= 1.8v; vss1=vss2=vss3 =vss4=0v; fs=44.1khz, bick=64fs; signal frequency=1khz; 24bit data; measurement frequency=20hz 20khz; unless otherwise specified) parameter min typ max unit mic amplifier: lin1, rin1, lin2, rin2 pins input resistance 23 33 43 k mgain3-0 bits = ?0000? -1 0 +1 db mgain3-0 bits = ?0001? +4 +5 +6 db mgain3-0 bits = ?0010? +7 +8 +9 db gain mgain3-0 bits = ?0011? +10 +11 +12 db mgain3-0 bits = ?0100? +13 +14 +15 db mgain3-0 bits = ?0101? +15 +16 +17 db mgain3-0 bits = ?0110? +17 +18 +19 db mgain3-0 bits = ?0111? +20 +21 +22 db mgain3-0 bits = ?1000? +23 +24 +25 db mic power supply: mpwr pin micl bit = ?0? 2.3 2.5 2.7 v output voltage ( note 8 ) micl bit = ?1? 2.0 2.2 2.4 v output noise level (a-weighted) - ? 108 - dbv load resistance 0.5 - - k load capacitance - - 30 pf psrr (fin =1khz) - 100 - db adc analog input characteristics : lin1/rin1/lin2/rin2 pins adc ivol, ivol=0db, alc=off resolution/ - - 24 bits ( note 10 ) - 0.261 - vpp input voltage ( note 9) ( note 11 ) 1.86 2.07 2.28 vpp ( note 10 ) 73 83 - dbfs s/(n+d) ( ? 1dbfs) ( note 11 ) - 85 - dbfs ( note 10 ) 78 88 - db d-range ( ? 60dbfs, a-weighted) ( note 11 ) - 96 - db ( note 10 ) 78 88 - db s/n (a-weighted) ( note 11 ) - 96 - db ( note 10 ) 75 90 - db interchannel isolation ( note 11 ) - 100 - db ( note 10 ) - 0 0.5 db interchannel gain mismatch ( note 11 ) - 0 0.5 db note 8. avdd should be in the range of 2.7 ~ 3.6v when micl bit is ?1?. it should be in the range of 3.0~3.6v when micl bit is ?0?. note 9. vin = 0.9 x 2.3vpp (typ) @mgain3-0 bits = ?0000? (0db) note 10. mgain3-0 bits = ?0110? (+18db) note 11. mgain3-0 bits = ?0000? (0db)
[AK4950] ms1320-e-00 2011/10 - 8 - parameter min typ max unit dac characteristics: resolution - - 24 bits stereo line output characteristics: dac lout, rout pins, alc= off, dvol=ovol =0db, lovl1-0 bit = ?01?, r l =10k , pmbp bit= ?0? lovl0 bit = ?1? 2.27 2.52 2.77 vpp output voltage ( note 12 ) lovl0 bit = ?0? 1.94 2.16 2.38 vpp s/(n+d) ( ? 3dbfs) 73 83 - dbfs s/n (a-weighted) 82 92 - db interchannel isolation 85 100 - db interchannel gain mismatch - - 0.8 db load resistance 10 - - k load capacitance - - 30 pf psrr (fin =1khz) - 80 - db speaker-amp characteristics: dac spp/spn pins, alc=o ff, dvol=ovol =0db, r l =8 , btl output voltage spkg1-0 bits = ?00?, ? 0.5dbfs (po=150mw) - 3.18 - vpp spkg1-0 bits = ?01?, ? 0.5dbfs (po=250mw) 3.20 4.00 4.80 vpp spkg1-0 bits = ?10?, ? 0.5dbfs (po=400mw) - 1.79 - vrms s/(n+d) spkg1-0 bits = ?00?, ? 0.5dbfs (po=150mw) - 75 - db spkg1-0 bits = ?01?, ? 0.5dbfs (po=250mw) 20 70 - db spkg1-0 bits = ?10?, ? 0.5dbfs (po=400mw) - 65 - db s/n spkg1-0 bits = ?01?, ? 0.5dbfs(po=250mw) (a-weighted) 85 95 - db load resistance 6.8 - - load capacitance - - 30 pf psrr (fin =1khz) - 60 - db note 12. avdd should be in the range of 3.0~3.6v when lovl0 bit is ?1?. it should be in the range of 2.7~3.6v when lovl0 bit is ?0?.
[AK4950] ms1320-e-00 2011/10 - 9 - parameter min typ max unit mono input: min pin, external resistance mode (pmbp bit =?1?, bpm bit = ?1?, bpvcm bit = ?0?, bp lvl2-0 bits = ?000?), external input resistance= 66k maximum input voltage ( note 13 ) - 1.54 - vpp gain ( note 14 ) min ? lout lovl1-0 bit = ?00? ? 4.5 0 +4.5 db lovl1-0 bit = ?01? - +1.34 - db lovl1-0 bit = ?10? - +2 - db lovl1-0 bit = ?11? - +3.34 - db min ? spp/spn alc bit = ?0?, spkg1-0 bits = ?00? +1.6 +6.1 +10.6 db alc bit = ?0?, spkg1-0 bits = ?01? - +8.1 - db alc bit = ?0?, spkg1-0 bits = ?10? - +10.1 - db alc bit = ?0?, spkg1-0 bits = ?11? - +12.1 - db alc bit = ?1?, spkg1-0 bits = ?00? - +8.1 - db alc bit = ?1?, spkg1-0 bits = ?01? - +10.1 - db alc bit = ?1?, spkg1-0 bits = ?10? - +12.1 - db alc bit = ?1?, spkg1-0 bits = ?11? - +14.1 - db mono input: min pin, internal resistance mode (pmbp bit =?1?, bpm bit = ?0? , bpvcm bit = ?0?, bplvl2-0 bits = ?000?) input resistance 56 66 76 k maximum input voltage ( note 13 ) - 1.54 - vpp gain min ? lout lovl1-0 bit = ?00? -1 0 +1 db lovl1-0 bit = ?01? - +1.34 - db lovl1-0 bit = ?10? - +2 - db lovl1-0 bit = ?11? - +3.34 - db min ? spp/spn alc bit = ?0?, spkg1-0 bits = ?00? +4.1 +6.1 +8.1 db alc bit = ?0?, spkg1-0 bits = ?01? - +8.1 - db alc bit = ?0?, spkg1-0 bits = ?10? - +10.1 - db alc bit = ?0?, spkg1-0 bits = ?11? - +12.1 - db alc bit = ?1?, spkg1-0 bits = ?00? - +8.1 - db alc bit = ?1?, spkg1-0 bits = ?01? - +10.1 - db alc bit = ?1?, spkg1-0 bits = ?10? - +12.1 - db alc bit = ?1?, spkg1-0 bits = ?11? - +14.1 - db note 13. the maximum value is avdd vpp when bpvcm bit = ?1?. however, it must be set that the output level of min-amp is less than 0.1vpp by setting bplvl2-0 bits. note 14. the gain is in inverse proportion to external input resistance.
[AK4950] ms1320-e-00 2011/10 - 10 - parameter min typ max unit video signal input external resistor ( note 16 ) r1 ( figure 2 ) - - 600 external capacitor c1 ( figure 2 ) 0.05 0.1 0.2 f maximum input voltage: vg1-0 bits = ?00? (+6db) - 1.0 1.24 vpp pull down current - 0.4 - a video analog output ( figure 3 ) vg1-0 bits = ?00?, 1.0vpp input 5.5 6.0 6.5 vg1-0 bits = ?01?, 0.7vpp input 8.5 9.0 9.5 vg1-0 bits = ?10?, 0.5vpp input 11.5 12.0 12.5 output gain fin=100khz sine wave input ( note 15 ) vg1-0 bits = ?11?,0.3vpp input 16 16.5 17 db signal input (pedestal level) ? 100 0 100 mv dc output offset level ( note 15 ) no signal input - ? 572 - mv s/n( note 17 ) vg1-0 bits = ?00?(+6db) bw = 100kh 6mhz, s = 0.7vpp input 58 70 - db maximum output voltage ( note 15 ) fin = 100khz (sine wave) 2.62 - - vpp secondary harmonic distortion vg1-0 bits = ?00?(+6db), f = 3.58mhz, 1.0vpp: ? 40 ~ 100ire, sine wave input - ? 40 ? 30 db load resistance 140 150 - load capacitance c2 ( figure 3 ) c3 ( figure 3 ) - - - - 15 400 pf pf fin = 10khz - 60 - db psrr vg1-0 bits = ?00?(+6db) fin = 100khz - 45 - db lpf for vin signal : ( note 15 ) frequency response (f = 100khz, 1.0vpp, sine wave input) response at 6.75mhz ? 3.0 0 +1.5 response at 27mhz - ? 40 ? 30 db group delay |gd3mhz ? gd6mhz| - 10 100 ns note 15. this is a value at measurement point in figure 3 . 1.0vpp input is the value when vg1-0 bits =?00?. input amplitude is in inverse proportion to the gain. s/n is measured at measurement point 2. note 16. pmv bit must be set to ?0? if the input impedance of the vin pin exceeds 600 ? when the input signal is stopped or when the vin pin input circuit is powered down. note 17. s/n = 20xlog (output voltage[vpp]/noise level[vrms]). output voltage = 0.7 [vpp]. AK4950 vin pin r1 from video dac c1 figure 2. external resistor of video signal input pin video signal output 75 ohm 75 ohm c3 r2 r3 c2 measurement point1 measurement point2 figure 3. load capacitance c2 and c3
[AK4950] ms1320-e-00 2011/10 - 11 - parameter min typ max unit power supplies: power up (pdn pin = ?h?) all circuit power-up ( note 18 ) avdd+tvdd - 22.2 33 ma mic + adc ( note 15 ) avdd+tvdd - 5.5 - ma dac + lineout ( note 16 ) avdd+tvdd - 5.2 - ma dac + spk-amp avdd+tvdd - 6 - ma video block ( note 22 ) avdd - 12.7 19 ma power down (pdn pin = ?l?) ( note 17 ) avdd+tvdd - 1 5 a note 18. when pmadl=pmadr=pmdac=pmpfil =p mlo=pmspk=pmpll=mcko=pmbp=pmmp=m/s= pmv bits = ?1?, spk-amp no load, and black signal is only input to the vin pin in pll master mode (mcki=12mhz). in this case, the output current of the mpwr pin is 0ma. avdd=20.7ma (typ), tvdd=1.5ma (typ). note 19. when pmadl = pmadr bits= ?1? and pmpfil bit = ?1? in ext slave mode (pmpll=m/s=mcko bits =?0?). note 20. when pmdac = pmlo bits= ?1? and pmpfil bit = ?1? in ext slave mode (pmpll=m/s=mcko bits =?0?). note 21. when pmdac = pmspk =sppsn bits = ?1?, pmpfil b it = ?1?, and no load at spk-amp in ext slave mode (pmpll=m/s=mcko bits =?0?). note 22. when pmv=pmcp bits = ?1?, no-load, and the black signal is only input to the vin pin. note 23. all digital input pins are fixed to tvdd or vss2.
[AK4950] ms1320-e-00 2011/10 - 12 - filter characteristics (ta =25 c; avdd=2.7 3.6v, tvdd =1.6 3.6v; fs=44.1khz; dem=off) parameter symbol min typ max unit adc digital filter (decimation lpf): passband ( note 24 ) 0.16db pb 0 - 17.3 khz ? 0.66db - 19.4 - khz ? 1.1db - 19.9 - khz ? 6.9db - 22.1 - khz stopband ( note 24 ) sb 26.1 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 73 - - db group delay ( note 25 ) gd - 19 - 1/fs group delay distortion gd - 0 - s adc digital filter (hpf): hpfc1-0 bits = ?00? frequency response ? 3.0db fr - 3.4 - hz ? 0.5db - 10 - hz ? 0.1db - 22 - hz dac digital filter (lpf): passband ( note 24 ) 0.05db pb 0 - 20.0 khz ? 6.0db - 22.05 - khz stopband ( note 24 ) sb 24.1 - - khz passband ripple pr - - 0.02 db stopband attenuation sa 54 - - db group delay ( note 25 ) gd - 20 - 1/fs dac digital filter (lpf) + scf: frequency response: 0 20.0khz fr - 1.0 - db note 24. the passband and stopband frequencies scale with fs (s ystem sampling rate). each response refers to that of 1khz. for example, it is 0.454 x fs (adc) when pb=20.0khz (@ ? 1.0db). note 25. a calculating delay time which induced by digital filtering. this time is from the input of an analog signal to the setting of 24-bit data of both channels to the adc output register. for the dac, this time is from setting the 24-bit data of a channel from the input register to the output of analog signal. group delay time is the same as the value shown above even when a signal path that include s the programmable filters (1st order hpf + 1st order lpf + 3-band equalizer + alc + equalizer) is selected.
[AK4950] ms1320-e-00 2011/10 - 13 - dc characteristics (ta =25 c; avdd=2.7 3.6v, tvdd =1.6 3.6v; fs= 44.1khz; dem=off) parameter symbol min typ max unit audio interface & serial p interface (cdtio/cad0, csn/sda, cclk/scl, i2c, pdn, bick, lrck, sdti, mcki pins ) high-level input voltage (except i2c pin, tvdd 2.2v) (except i2c pin, tvdd < 2.2v) (i2c pin) low-level input voltage (except i2c pin, tvdd 2.2v) (except i2c pin, tvdd < 2.2v) (i2c pin) vih vih1 vil vil1 70%tvdd 80%tvdd 70%avdd - - - - - - - - - - - - 30%tvdd 20%tvdd 30%avdd v v v v v v audio interface & serial p interface (cdtio , sda mcko, bick, lrck, sdto pins output) high-level output voltage (iout = ? 80 a) low-level output voltage (except sda pin : iout = 80 a) (sda pin, 2.0v tvdd 3.6v: iout = 3ma) (sda pin, 1.6v tvdd < 2.0v: iout = 3ma) voh vol1 vol2 vol2 tvdd ? 0.2 - - - - - - - - 0.2 0.4 20%tvdd v v v v input leakage current iin - - 10 a digital mic interface (dmdat pin input ; dmic bit = ?1?) high-level input voltage low-level input voltage vih2 vil2 65%avdd - - - - 35%avdd v v digital mic interface (dmclk pin output ; dmic bit = ?1?) high-level output voltage (iout= ? 80 a) low-level output voltage (iout= 80 a) voh3 vol3 avdd-0.4 - - - - 0.4 v v input leakage current iin2 - - 20 a
[AK4950] ms1320-e-00 2011/10 - 14 - switching characteristics (ta =25 c; avdd=2.7 3.6v, tvdd =1.6 3.6v; c l =20pf) parameter symbol min typ max unit pll master mode (pll reference clock = mcki pin) mcki input timing frequency fclk 11.2896 - 27 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns mcko output timing frequency fmck 0.256 - 12.288 mhz duty cycle dmck 40 50 60 % lrck output timing frequency fs 8 - 48 khz duty cycle duty - 50 - % bick output timing period bcko bit = ?0? tbck - 1/(32fs) - ns bcko bit = ?1? tbck - 1/(64fs) - ns duty cycle dbck - 50 - % pll slave mode (pll reference clock = mcki pin) mcki input timing frequency fclk 11.2896 - 27 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns mcko output timing frequency fmck 0.256 - 12.288 mhz duty cycle dmck 40 50 60 % lrck input timing frequency fs 8 - 48 khz duty duty 45 - 55 % bick input timing period tbck 1/(64fs) - 1/(32fs) ns pulse width low tbckl 0.4 x tbck - - ns pulse width high tbckh 0.4 x tbck - - ns
[AK4950] ms1320-e-00 2011/10 - 15 - parameter symbol min typ max unit pll slave mode (pll reference clock = bick pin) lrck input timing frequency fs 7.35 - 48 khz duty duty 45 - 55 % bick input timing period pll3-0 bits = ?0010? tbck - 1/(32fs) - ns pll3-0 bits = ?0011? tbck - 1/(64fs) - ns pulse width low tbckl 0.4 x tbck - - ns pulse width high tbckh 0.4 x tbck - - ns external slave mode mcki input timing frequency 512fs fclk 3.7632 - 24.576 mhz 1024fs fclk 7.5264 - 13.312 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns lrck input timing frequency 512fs fs 7.35 - 48 khz 1024fs fs 7.35 - 13 khz duty duty 45 - 55 % bick input timing period tbck 312.5 - - ns pulse width low tbckl 130 - - ns pulse width high tbckh 130 - - ns external master mode mcki input timing frequency 512fs fclk 3.7632 - 24.576 mhz 1024fs fclk 7.5264 - 13.312 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns lrck output timing frequency fs 7.35 - 48 khz duty cycle duty - 50 - % bick output timing period bcko bit = ?0? tbck - 1/(32fs) - ns bcko bit = ?1? tbck - 1/(64fs) - ns duty cycle dbck - 50 - %
[AK4950] ms1320-e-00 2011/10 - 16 - parameter symbol min typ max unit audio interface timing master mode bick ? ? to lrck edge ( note 26 ) tmblr ? 40 - 40 ns lrck edge to sdto (msb) (except i 2 s mode) tlrd ? 70 - 70 ns bick ? ? to sdto tbsd ? 70 - 70 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns slave mode lrck edge to bick ? ? ( note 26 ) tlrb 50 - - ns bick ? ? to lrck edge ( note 26 ) tblr 50 - - ns lrck edge to sdto (msb) (except i 2 s mode) tlrd - - 80 ns bick ? ? to sdto tbsd - - 80 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns control interface ti ming (3-wire mode): cclk period tcck 200 - - ns cclk pulse width low tcckl 80 - - ns pulse width high tcckh 80 - - ns cdtio setup time tcds 40 - - ns cdtio hold time tcdh 40 - - ns csn ?h? time tcsw 150 - - ns csn edge to cclk ? ? ( note 27 ) tcss 50 - - ns cclk ? ? to csn edge ( note 27 ) tcsh 50 - - ns cclk ? ? to cdtio (at read command) tdcd - - 70 ns csn ? ? to cdtio (hi-z) (at read command)( note 29 ) tccz - - 70 ns control interface timing (i 2 c bus mode): scl clock frequency fscl - - 400 khz bus free time between transmissions tbuf 1.3 - - s start condition hold time (prior to first clock pulse) thd:sta 0.6 - - s clock low time tlow 1.3 - - s clock high time thigh 0.6 - - s setup time for repeated start condition tsu:sta 0.6 - - s sda hold time from scl falling ( note 30 ) thd:dat 0 - - s sda setup time from scl rising tsu:dat 0.1 - - s rise time of both sda and scl lines tr - - 0.3 s fall time of both sda and scl lines tf - - 0.3 s setup time for stop condition tsu:sto 0.6 - - s capacitive load on bus cb - - 400 pf pulse width of spike noise suppre ssed by input filter tsp 0 - 50 ns note 26. bick rising edge must not occur at the same time as lrck edge. note 27. cclk rising edge must not occur at the same time as csn edge. note 28. i 2 c-bus is a trademark of nxp b.v. note 29. it is the time of 10% potential change of the cdtio pin when r l =1k (pull-up or tvdd). note 30. data must be held for sufficient tim e to bridge the 300 ns transition time of scl.
[AK4950] ms1320-e-00 2011/10 - 17 - parameter symbol min typ max unit digital audio interface timing; c l =100pf dmclk output timing period tsck - 1/(64fs) - ns rising time tsrise - - 10 ns falling time tsfall - - 10 ns duty cycle dsck 40 50 60 % audio interface timing dmdat setup time tsds 50 - - ns dmdat hold time tsdh 0 - - ns power-down & reset timing pdn pulse width ( note 31 ) tpd 150 - - ns pmadl or pmadr ? ? to sdto valid ( note 32 ) adrst bit = ?0? tpdv - 1059 - 1/fs adrst bit = ?1? tpdv - 267 - 1/fs note 31. the AK4950 can be reset by the pdn pin = ?l?. when restart the AK4950 after powered-down, set the pdn pin to ?l? and change to ?h? after a 10ms interval. note 32. this is the count of lrck ? ? from the pmadl or pmadr bit = ?1?.
[AK4950] ms1320-e-00 2011/10 - 18 - timing diagram lrck 1/fclk mcki tclkh tclkl vih vil 1/fmck mcko tmckl 50%tvdd 1/fs tlrckh tlrckl 50%tvdd duty = tlrckh x fs x 100 tlrckl x fs x 100 dmck = tmckl x fmck x 100 note 33. mcko is not available at ext master mode. figure 4. clock timing (pll/ext master mode) lrck 50%tvdd bick 50%tvdd sdto 50%tvdd tbsd tsds sdti vil tsdh vih tblr tbckl tdlr figure 5. audio interface ti ming (pll/ext master mode)
[AK4950] ms1320-e-00 2011/10 - 19 - 1/fclk mcki tclkh tclkl vih vil 1/fs lrck vih vil tbck bick tbckh tbckl vih vil tlrckh tlrckl fmck mcko tmckl 50%tvdd dmck = tmckl x fmck x 100 duty = tlrckh x fs x 100 = tlrckl x fs x 100 figure 6. clock timing (pll slave mode; pll reference clock = mcki pin) 1/fclk mcki tclkh tclkl vih vil 1/fs lrck vih vil tbck bick tbckh tbckl vih vil tlrckh tlrckl duty = tlrckh x fs x 100 tlrckl x fs x 100 figure 7. clock timing (ext slave mode)
[AK4950] ms1320-e-00 2011/10 - 20 - lrck vih vil tblr bick vih vil tlrd sdto 50%tvdd tlrb tbsd tsds sdti vil tsdh vih msb figure 8. audio interface timing (pll/ext slave mode) csn vih vil tcss cclk tcds vih vil cdtio vih tcckh tcckl tcdh vil r/w a6 a5 tcck tcsh figure 9. write command input timing
[AK4950] ms1320-e-00 2011/10 - 21 - csn vih vil tcsh cclk vih vil cdtio vih tcsw vil d1 d0 d2 tcss figure 10. write data input timing csn cclk 50% tvdd cdtio vih d3 d2 d1 d0 tccz tdcd vil vih vil hi-z clock, h or l figure 11. read data output timing
[AK4950] ms1320-e-00 2011/10 - 22 - stop start start stop thigh thd:dat sda scl tbuf tlow tr tf tsu:dat vih vil thd:sta tsu:sta vih vil tsu:sto tsp figure 12. i 2 c bus mode timing tsck 65%avdd dmclk 35%avdd tsckl 50%avdd dsck = 100 x tsckl / tsck tsrise tsfall figure 13. dmclk clock timing dmclk 65%avdd dmdat tsds vih3 vil3 tsdh 35%avdd figure 14. audio interface timing (dclkp bit = ?1?) figure 15. audio interface timing (dclkp bit = ?0?) dmclk 65%avdd dmdat tsds vih3 vil3 tsdh 35%avdd
[AK4950] ms1320-e-00 2011/10 - 23 - pmadl bit or pmadr bit tpdv sdto 50%tvdd figure 16. power down & reset timing 1 tpd pdn vil figure 17. power down & reset timing 2
[AK4950] ms1320-e-00 2011/10 - 24 - operation overview system clock there are the following five clock modes to interface with external devices ( table 1 , table 2 ). mode pmpll bit m/s bit pll3-0 bits figure pll master mode ( note 34 ) 1 1 table 4 figure 18 pll slave mode 1 (pll reference clock: mcki pin) 1 0 table 4 figure 19 pll slave mode 2 (pll reference clock: lrck or bick pin) 1 0 table 4 figure 20 ext slave mode 0 0 x figure 21 ext master mode 0 1 x figure 22 note 34. if m/s bit = ?1?, pmpll bit = ?0? and mcko bit = ?1? during the setting of pll master mode, the invalid clocks are output from the mcko pin. table 1. clock mode setting (x: don?t care) mode mcko bit mcko pin mcki pin bick pin lrck pin 0 l pll master mode 1 selected by ps1-0 bits selected by pll3-0 bits output (selected by bcko bit) output (1fs) 0 l pll slave mode (pll reference clock: mcki pin) 1 selected by ps1-0 bits selected by pll3-0 bits input ( 32fs) input (1fs) pll slave mode (pll reference clock: bick pin) 0 l gnd input ( 32fs) input (1fs) ext slave mode 0 l selected by fs3-0 bits input ( 32fs) input (1fs) ext master mode 0 l selected by fs1-0 bits output (selected by bcko bit) output (1fs) note 35. when pmvcm bit = m/s bit = ?1? and mcki is input, lrck and bick are output even if pmdac=pmadl= pmadr bits = ?0?. table 2. clock pins state in clock mode master mode/slave mode the m/s bit selects either master or sl ave mode. m/s bit = ?1? selects master m ode and ?0? selects slave mode. when the AK4950 is in power-down mode (pdn pin = ?l?) and when exits reset state, the AK4950 is in slave mode. after exiting reset state, the AK4950 goes to master mode by changing m/s bit to ?1?. when the AK4950 is in master mode, the lrck and bick pins are a floating state until m/s bit becomes ?1?. the lrck and bick pins of the AK4950 must be pulled-down or pulled-up by a resistor (about 100k ) externally to avoid the floating state. m/s bit mode 0 slave mode (default) 1 master mode table 3. select master/slave mode
[AK4950] ms1320-e-00 2011/10 - 25 - pll mode when pmpll bit is ?1?, a fully integrated analog phase locked loop (pll) circuit generates a clock that is selected by the pll3-0 and fs3-0 bits. the pll lock times, when the ak 4950 is supplied stable clocks after pll is powered-up (pmpll bit = ?0? ?1?) or the sampling frequency is changed, are shown in table 4 . 1) pll mode setting mode pll3 bit pll2 bit pll1 bit pll0 bit pll reference clock input pin input frequency pll lock time (max) 2 0 0 1 0 bick pin 32fs 2 ms 3 0 0 1 1 bick pin 64fs 2 ms 4 0 1 0 0 mcki pin 11.2896mhz 10 ms 6 0 1 1 0 mcki pin 12mhz 10 ms (default) 7 0 1 1 1 mcki pin 24mhz 10 ms 12 1 1 0 0 mcki pin 13.5mhz 10 ms 13 1 1 0 1 mcki pin 27mhz 10 ms others others n/a note 36. the resistor tolerance is 5% and the capacitor tolerance is 30%. table 4. pll mode setting (*fs: sampling frequency, n/a: not available) 2) setting of sampling frequency in pll mode when pll2 bit is ?1? (pll reference clock input is mcki pin), the sampling frequency is selected by fs3-0 bits as defined in table 5 . mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency 0 0 0 0 0 8khz 1 0 0 0 1 12khz 2 0 0 1 0 16khz 3 0 0 1 1 24khz 5 0 1 0 1 11.025khz 7 0 1 1 1 22.05khz 10 1 0 1 0 32khz 11 1 0 1 1 48khz 15 1 1 1 1 44.1khz (default) others others n/a table 5. setting of sampling frequency at pll2 bit = ?1? and pmpll bit = ?1? (reference clock = mcki pi n), (n/a: not available) when pll2 bit is ?0? (pll reference clock input pin is the bick pin), the sampling frequency is selected by fs1-0 bits. ( table 6 ). * since the default setting of fs3-0 bits is ?1111? (not available), fs3-0 bits must be set when pll2 bit = ?0?. mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency range 0 0 0 x x 7.35khz d fs d 12khz 1 0 1 x x 12khz < fs d 24khz 2 1 0 x x 24khz < fs d 48khz others others n/a (default) table 6. setting of sampling frequency at pll2 bit = ?0? and pmpll bit = ?1? pll slave mode 2 (pll reference clock: bick pin), (x: don?t care, n/a: not available)
[AK4950] ms1320-e-00 2011/10 - 26 - pll unlock state 1) pll master mode (pmpll bit = ?1?, m/s bit = ?1?) in this mode, the lrck and bick pins go to ?l?, and irregular frequency clock is output from the mcko pin when mcko bit is ?1? before the pll goes to lock state after pmpll bit = ?0? ?1?. if mcko bit is ?0?, the mcko pin outputs ?l? ( table 7 ). after the pll is locked, a first period of lrck and bick may be invalid clock, but these clocks return to normal state after a period of 1/fs. the bick and lrck pins do not output irregular frequency cl ocks such as pll unlock state by setting pmpll bit to ?0?. during pmpll bit = ?0?, these pins output the same clocks as ext master mode. mcko pin pll state mcko bit = ?0? mcko bit = ?1? bick pin lrck pin after pmpll bit ?0? ?1? ?l? output invalid ?l? output ?l? output pll unlock (except the case above) ?l? output invalid invalid invalid pll lock ?l? output table 9 table 10 1fs output table 7. clock operation at pll master mode (pmpll bit = ?1?, m/s bit = ?1?) 2) pll slave mode (pmpll b it = ?1?, m/s bit = ?0?) in this mode, an invalid clock is output from the mcko pin before the pll goes to lock state after pmpll bit = ?0? ?1?. then, the clock selected by table 9 is output from the mcko pin when pll is locked. adc and dac output invalid data when the pll is unlocked. the dac outputs can be muted by setting dacl and dacs bits to ?0?. mcko pin pll state mcko bit = ?0? mcko bit = ?1? after pmpll bit ?0? ?1? ?l? output invalid pll unlock (except the case above) ?l? output invalid pll lock ?l? output output table 8. clock operation at pll slave mode (pmpll bit = ?0?, m/s bit = ?0?)
[AK4950] ms1320-e-00 2011/10 - 27 - pll master mode (pmpll bit = ?1?, m/s bit = ?1?) when an external clock (11.2896mhz, 12mhz, 13.5mhz, 24mhz or 27mhz) is input to the mcki pin, the internal pll circuit generates mcko, bick and lrck clocks. the mcko output frequency is selected by ps1-0 bits ( table 9 ) and the output is enabled by mcko bit. the bick output frequency is selected between 32fs or 64fs, by bcko bit ( table 10 ). AK4950 dsp or p mcko bick lrck sdto sdti bclk lrck sdti sdto mcki 1f s 32fs, 64fs 256fs/128fs/64fs/32fs 11.2896mhz,12mhz, 13.5mhz, 24mhz, 25mhz, 27mhz mclk figure 18. pll master mode mode ps1 bit ps0 bit mcko pin 0 0 0 256fs (default) 1 0 1 128fs 2 1 0 64fs 3 1 1 32fs table 9. mcko output frequency (pll mode, mcko bit = ?1?) bcko bit bick output frequency 0 32fs (default) 1 64fs table 10. bick output frequency at master mode
[AK4950] ms1320-e-00 2011/10 - 28 - pll slave mode (pmpll bit = ?1?, m/s bit = ?0?) a reference clock of pll is selected among the input clocks to the mcki, bick or lrck pins. the required clock for the AK4950 is generated by an internal pll circuit. input frequency is selected by pll3-0 bits ( table 4 ). a) pll reference clock: mcki pin the bick and lrck inputs must be synchronized with mcko output. the phase between mcko and lrck is not important. the mcko pin outputs the frequency selected by ps1-0 bits ( table 9 ) and the output is enabled by mcko bit. sampling frequency can be selected by fs3-0 bits ( table 5 ) AK4950 dsp or p mcko bick lrck sdto sdti bclk lrck sdti sdto mcki 1fs 32fs 11.2896mhz, 12mhz, 13.5mhz, 24mhz, 27mhz mclk 256fs/128fs/64fs/32fs figure 19. pll slave mode 1 (pll reference clock: mcki pin) b) pll reference clock: bick pin the sampling frequency corresponds to a range fro m 7.35khz to 48khz by changing fs3-0 bits ( table 6 ). AK4950 dsp or p mcki bick lrck sdto sdti bclk lrck sdti sdto mcko 1fs 32fs or 64fs figure 20. pll slave mode 2 (pll reference clock: bick pin)
[AK4950] ms1320-e-00 2011/10 - 29 - ext slave mode (pmpll bit = ?0?, m/s bit = ?0?) when pmpll bit is ?0?, the AK4950 becomes ext mode. master clock can be input to the internal adc and dac directly from the mcki pin without internal pll circuit operation. this mode is compatible with i/f of a normal audio codec. the external clocks required to operate this mode are mcki (512fs or 1024fs), lrck (fs) and bick ( 32fs). the master clock (mcki) must be synchronized with lrck. the phase between these clocks is not important. the input frequency of mcki is selected by fs1-0 bits ( table 11 ). mode fs3-2 bits fs1 bit fs0 bit mcki input frequency sampling frequency range 1 x 0 1 1024fs 7.35khz 13khz 2 x 1 0 512fs 7.35khz 26khz 3 x 1 1 512fs 7.35khz 48khz (default) others others n/a n/a (x: don?t care, n/a: not available) table 11. mcki frequency at ext slave mode (pmpll bit = ?0?, m/s bit = ?0?) the s/n of the dac at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. the out-of-band noise can be reduced by using higher frequenc y of the master clock. the s/n of the dac output through lout/rout pins is shown in table 12 . mcki s/n (fs=8khz, 20khzlpf + a-weighted) mode3; 512fs 80db mode2; 512fs 92db mode1; 1024fs 92db table 12. relationship between mcki and s/n of lout/rout pins AK4950 dsp or p mcki bick lrck sdto sdti bclk lrck sdti sdto mcko 1fs 32fs mclk 512fs or 1024fs figure 21. ext slave mode
[AK4950] ms1320-e-00 2011/10 - 30 - ext master mode (pmpll bit = ?0?, m/s bit = ?1?) the AK4950 becomes ext master mode by setting pmpll bit = ?0 ? and m/s bit = ?1?. master clock can be input to the internal adc and dac directly from the mcki pin without the internal pll circuit operation. the external clock required to operate the AK4950 is mcki (512fs or 1024fs). the input frequency of mcki is selected by fs1-0 bits ( table 13 ). mode fs3-2 bits fs1 bit fs0 bit mcki input frequency sampling frequency range 1 x 0 1 1024fs 7.35khz 13khz 2 x 1 0 512fs 7.35khz 26khz 3 x 1 1 512fs 7.35khz 48khz (default) others others n/a n/a (x: don?t care, n/a: not available) table 13. mcki frequency at ext master mode (pmpll bit = ?0?, m/s bit = ?1?) the s/n of the dac at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. the out-of-band noise can be reduced by using higher frequenc y of the master clock. the s/n of the dac output through lout/rout pins is shown in table 14 . mcki s/n (fs=8khz, 20khzlpf + a-weighted) mode3; 512fs 80db mode2; 512fs 92db mode1; 1024fs 92db table 14. relationship between mcki and s/n of lout/rout pins AK4950 dsp or p mcki bick lrck sdto sdti bclk lrck sdti sdto mcko 1fs 32fs or 64fs mclk 512fs or 1024fs figure 22. ext master mode bcko bit bick output frequency 0 32fs (default) 1 64fs table 15. bick output frequency at master mode
[AK4950] ms1320-e-00 2011/10 - 31 - system reset upon power-up, the AK4950 must be reset by bringing the pdn pin = ?l?. it ensures that all internal registers are initialized. when restart the AK4950 after powered-down, the pdn pin should be se t to ?l? and hold 10ms. then set the pdn pin to ?h?, and init bit should be set to ?1? after clocks are input. it is recommended to set the pdn pin = ?l? before power up the AK4950. the adc starts an initialization cycle if the one of pmadl or pmadr bit is set to ?1? when both of the pmadl and pmadr bits are ?0?. the initialization cycle is set by adrst bit ( table 16 ). during the initialization cycle, the adc digital data outputs of both channels are forced to ?0? in 2's complement. the adc output reflects the analog input signal after the initialization cycle is finished . when using a digital microphone, the initia lization cycle is the same as adc?s. (note) the initial data of adc has offset data that de pends on microphones and the cut-off frequency of hpf. if this offset is not small, make initializa tion cycle longer by setting adrst bit or do not use the first data of adc outputs. init cycle adrst bit cycle fs = 8khz fs = 16khz fs = 44.1khz 0 1059/fs 132.4ms 66.2ms 24ms 1 267/fs 33.4ms 16.7ms 6.1ms table 16. adc initialization cycle audio interface format four types of data formats are available and selected by setting the dif1-0 bits ( table 17 ). in all modes, the serial data is msb first, 2?s complement format. audio interface formats are supported in both master and slave modes. lrck and bick are output from the AK4950 in master mode, but must be input to the AK4950 in slave mode. the sdto is clocked out on the falling edge (? ?) of bick and the sdti is latched on the rising edge (? ?) of bick. mode dif1 bit dif0 bit sdto (adc) sdti (dac) bick figure 0 0 0 24bit msb justified 24bit lsb justified 48fs figure 23 1 0 1 24bit msb justified 16bit lsb justified 32fs figure 24 2 1 0 24bit msb justified 24bit msb justified 48fs figure 25 (default) 3 1 1 i 2 s compatible i 2 s compatible =32fs or 48fs figure 26 table 17. audio interface format
[AK4950] ms1320-e-00 2011/10 - 32 - lrck bick(64fs) sdto ( o ) 0 1 2 8 9 10 20 21 31 0 1 2 8 9 10 20 21 31 0 23 1 22 0 23 22 16 15 14 0 23 sdti(i) 1 22 0 23 12 11 1 22 0 23 12 11 23:msb, 0:lsb lch data rch data don?t care don?t care 16 15 14 figure 23. mode 0 timing lrck bick ( 64fs ) sdto(o) 0 1 2 3 15 16 17 18 0 1 2 3 15 16 18 17 31 1 sdti ( i ) 23 24 30 23 24 25 23 22 8 13 8 15 14 24bit: 23:msb, 0:lsb 16bit: 15: msb, 0:lsb lch data rch data don?t care 21 5 0 7 6 bick(32fs) sdto ( o ) 0 1 2 3 7 8 9 10 0 1 2 3 15 9 11 10 0 1 sdti(i) 12 13 14 12 13 14 22 21 22 21 10 823 9 15 14 13 12 11 15 23 10 8 9 15 14 13 12 11 8 23 14 13 14 13 2 015 1 7 6 5 4 3 15 2 0 1 7 6 5 4 3 15 0 21 31 23 22 8 13 8 15 14 21 5 0 76 0 2 1 30 don?t care 23 figure 24. mode 1 timing lrck bclk(64fs) sdto ( o ) 0 1 2 18 19 20 21 22 0 1 2 18 19 20 22 21 0 1 sdti(i) 23 24 25 23 24 25 23 22 4 23 22 5 4 5 4 1 22 0 23 3 2 1 22 0 23 3 2 23:msb, 0:lsb lch data rch data don?t care don?t care 5 5 4 1 0 32 10 3 2 23 figure 25. mode 2 timing
[AK4950] ms1320-e-00 2011/10 - 33 - lrck bick ( 64fs ) sdto(o) 0 1 2 3 19 20 21 22 0 1 2 3 19 20 22 21 0 1 sdti ( i ) 23 24 25 23 24 25 23 22 4 23 22 5 4 5 4 1 22 0 23 3 2 1 22 0 23 3 2 23:msb, 0:lsb lch data rch data don?t care don?t care 5 5 4 1 0 3 2 10 3 2 bick(32fs) sdto ( o ) 0 1 2 3 7 8 9 10 0 1 2 3 15 9 11 10 0 1 sdti(i) 12 13 14 12 13 14 23 22 23 22 11 98 10 16 15 14 13 12 15 8 11 9 10 16 15 14 13 12 8 8 23 22 23 22 11 98 10 16 15 14 13 12 8 11 9 10 16 15 14 13 12 8 figure 26. mode 3 timing mono/stereo mode pmadl, pmadr, pmdml and pmdmr bits set mono/stereo adc operation. when changing adc operation and analog/digital microphone, pmadl, pmadr, pmdml and pmdmr bits must be set ?0? at first. when pmdml or pmdmr bit = ?1?, the setting of pmadl and pmadr bits is ignored. pmadl bit pmadr bit adc lch data adc rch data 0 0 all ?0? all ?0? (default) 0 1 rch input signal rch input signal 1 0 lch input signal lch input signal 1 1 lch input signal rch input signal table 18. mono/stereo adc operation (analog mic) pmdml bit pmdmr bit adc lch data adc rch data 0 0 all ?0? all ?0? (default) 0 1 rch input signal rch input signal 1 0 lch input signal lch input signal 1 1 lch input signal rch input signal table 19. mono/stereo adc operation (digital mic)
[AK4950] ms1320-e-00 2011/10 - 34 - mic/line input selector the AK4950 has an input selector. inl and inr bits select lin1/lin2 and rin1/rin2, respectively. when dmic bit = ?1?, digital microphone input is selected regardless of inl and inr bits. dmic bit inl bit inr bit lch rch 0 0 lin1 rin1 (default) 0 1 lin1 rin2 1 0 lin2 rin1 0 1 1 lin2 rin2 0 0 0 1 1 0 1 1 1 digital microphone table 20. mic/line in path select (x: don?t care, n/a: not available) mic gain amplifier the AK4950 has a gain amplifier for microphone input. the gain of mic-amp is selected by the mgain3-0 bits ( table 21 ). the typical input impedance is 30k . mgain3 bit mgain2 bit mgain1 bit mgain0 bit input gain 0 0 0 0 0db 0 0 0 1 +5db 0 0 1 0 +8db 0 0 1 1 +11db 0 1 0 0 +14db 0 1 0 1 +16db 0 1 1 0 +18db (default) 0 1 1 1 +21db 1 0 0 0 +24db others n/a (n/a: not available) table 21. input gain
[AK4950] ms1320-e-00 2011/10 - 35 - mic sensitivity compensation the AK4950 has microphone sensitivity (inter-channel gain mismatch) compensation function controlled by msgainl3-0 bits (lch) and msgainr3-0 bits (rch) msgainl3-0 bits msgainr3-0 bits gain (db) step 0111 +5.25 0110 +4.50 0101 +3.75 0100 +3.00 0011 +2.25 0010 +1.50 0001 +0.75 0000 0 (default) 1111 ?0.75 1110 ?1.50 1101 ?2.25 1100 ?3.00 1011 ?3.75 1010 ?4.50 1001 ?5.25 1000 ?6.00 0.75db table 22. mic sensitivity compensation mic sensitivity compensation gain can be written directly to the dsp by setting 01h and 02h (in 3-wire mode) or 81h and 82h (in i 2 c mode) without setting magainl /r3-0 bits. in this case, the gain can be set in a step less than 0.1db. the target gain is y[db], x=10 (y[db]/20) x 2 20 (y[db] +18db) available gain setting range: - gain < +18db (the coefficient has a 20-bit accuracy) round x off to the closest whole number and convert it to two?s complement. msb of the mic sensitivity compensation register is a sign bit. e.g.) mic sensitivity compensation value = -3.0[db] x = 10 (-3/20) x 2 20 = 742335 742335(dec) = 0b53be(hex): register value to be written the following is an access sequence to register map 2. sequence example (3-wire mode): 1. pmpfil bit = ?0? 2. init bit = ?1? 3. coew bit = ?1? 4. addr=01h, data=xxxxxxh(24bit data); lc h mic sensitivity compensation value 5. addr=02h, data=xxxxxxh(24bit data); rc h mic sensitivity compensation value 6. coew bit = ?0? 7. pmpfil bit = ?1?; programmable block power up (note) when accessing to the dsp directly on the a ddress 01h, 02h (in 3-wire mode) or 81h, 82h (in i 2 c mode), do not access to msgainl/r3-0 bits of the address 2bh.
[AK4950] ms1320-e-00 2011/10 - 36 - mic power when pmmp bit = ?1?, the mpwr pin supplies the power for microphones. this output voltage is typically 2.5v @micl bit =?0? (avdd=3.0 ~ 3.6v), and typically 2.2v@mic l bit = ?1? (avdd=2.7 ~ 3.6v). the load resistance is minimum 0.5k . in case of using two sets of stereo microphones, the load resistance is minimum 2k for each channel. any capacitor must not be connected directly to the mpwr pin ( figure 27 ). the mic power performance is deteriorat ed considerably when output the mic power and spk-amp at the same time since the mpwr pin output uses vss3 (spk-amp vss). simultaneous operation of mic power and spk-amp is not recommended. pmmp bit mpwr pin 0 hi-z (default) 1 output table 23. mic power mpwr pin figure 27. mic block circuit
[AK4950] ms1320-e-00 2011/10 - 37 - digital mic 1. connection to digital microphones when dmic bit is set to ?1?, the lin1 and rin1 pins become dmdat (digital microphone data input) and dmclk (digital microphone clock supply) pins respectively. the same voltage as avdd must be provided to the digital microphone. the figure 28 and figure 29 show stereo/mono connection examples. the dmclk clock is input to a digital microphone from the AK4950. the digital microphone outputs 1bit data, which is generated by ? modulator using dmclk clock, to the dmdat pin. pmdml/r bits control power up/down of the digital block (decimation filter and digital filter). pmadl/pmadr bits settings do not affect the digital microphone power management. the dclke bit controls on/off of the output clock from the dmclk pin. when the AK4950 is powered down (pdn pin= ?l?), the dmclk and dmdat pins become floating state. pull-down resistors must be connected to the dmclk and dmdat pins externally to avoid this floating state. amp ? modulator dmdat dmclk ( 64fs ) decimation filter pll mcki alc sdto programmable filter vdd AK4950 avdd 100k r amp ? modulator vdd lch rch hpf1 figure 28. connection example of stereo digital mic amp ? modulator dmdat dmclk ( 64fs ) decimation filter pll mcki alc sdto programmable filter vdd AK4950 avdd 1 00 k r hpf1 figure 29. connection example of mono digital mic
[AK4950] ms1320-e-00 2011/10 - 38 - 2. interface the input data channel of the dmdat pin is set by dclkp bit. when dclkp bit = ?1?, l channel data is input to the decimation filter if dmclk = ?h?, and r channel data is input if dmclk = ?l?. when dclkp bit = ?0?, r channel data is input to the decimation filter if dmclk = ?h?, and l channel data is input if dmclk = ?l?. the dmclk only supports 64fs. it outputs ?l? when dclke bit = ?0?, and outputs 64fs when dclke bit = ?1?. in this case, necessary clocks must be supplied to the AK4950 for adc operation. the output data through ?the decimation and digital filters? is 24bit full scale when the 1bit data density is 0%~100%. dclkp bit dmclk = ?h? dmclk = ?l? 0 rch lch (default) 1 lch rch table 24. data in/output timing with digital mic (dclkp bit = ?0?) dmclk(64fs) dmdat (lch) valid data valid data valid data valid data dmdat (rch) valid data valid data valid data valid data figure 30. data in/output timing with digital mic (dclkp bit = ?1?) dmclk(64fs) dmdat (lch) valid data valid data valid data valid data dmdat (rch) valid data valid data valid data valid data figure 31. data in/output timing with digital mic (dclkp bit = ?0?)
[AK4950] ms1320-e-00 2011/10 - 39 - digital block the digital block consists of the blocks shown in figure 32 . recording path and playback path is selected by setting adcpf bit, pfdac bit and pfsdo bit. ( figure 33 ~ figure 36 , table 25 ) dac 1st order hpf1 adc dvol sdti pfdac bit ?1? ?0? sdto hpfad bit pmadl/r bit adcpf bit ?1? ?0? alc (volume) 1st order hpf2 hpf bit 1st order lpf lpf bit stereo separation fil3 bit gain compensation eq0 bit gn1-0 bits 3 band eq eq4-2 bit alc bits 1 band eq eq1 bit pfsdo bit ?0? ?1? de-emphasis mono/stero switch mono1-0 bits pmdac bit smute : dsp block dem1-0 bits dvol7-0 bits smute bit pmpfil bit mic sensitivity compensation (1) adc: includes the digital filter (lpf) for adc as shown in ?filter chracteristics?. (2) hpf1: high pass filter (hpf) for adc as shown in ?filter chracteristics?. (3) mic sensitivity compensation: mic volume control between l and r channels. (see ? mic sensitivity compensation ?) (4) dac: includes the digital filter (lpf) for dac as shown in ?filter chracteristics?. (5) hpf2: high pass filter. applicable for use as wind-noise reduction filter. (see ? digital programmable filter circuit ?) (6) lpf: low pass filter (see ? digital programmable filter circuit ?) (7) stereo separation: stereo separation emphasis filter. (see ? digital programmable filter circuit ?) (8) gain compensation: gain compensation consists of eq a nd gain control. it corrects frequency characteristics after stereo separation emphasis filter. (see ? digital programmable filter circuit ?) (9) 3 band eq: applicable for use as equalizer or notch filter. (see ? digital programmable filter circuit ?) (10) volume: digital volume control with alc function. (see ? input digital volume ? and ? alc operation ?) (11) 1 band eq: applicable for use as equalizer or notch filter. (see ? digital programmable filter circuit ?) (12) dvol: digital volume for playback path (see ? output digital volume2 ? ) (13) smute: soft mute function (14) mono/stereo switching: mono/stereo lineout outputs select from dac which described in at ?stereo line outputs?. (15) de-emphasis: de-emphasis filter (see ?de-emphasis filter control?) figure 32. digital block path select
[AK4950] ms1320-e-00 2011/10 - 40 - mode adcpf bit pfdac bit pfsdo bit figure recording mode 1 1 0 1 figure 33 playback mode 1 0 1 0 figure 34 recording mode 2 & playback mode 2 x 0 0 figure 35 loopback mode 1 1 1 figure 36 table 25. recording playback mode (x: don?t care) when changing those modes, pmpfil bit must be ?0?. dac 1st order hpf2 adc 3 band eq alc (volume) smute 1st order lpf stereo separation gain compensation 1 band eq 1st order hpf1 mono dem dvol mic sensitivity correction figure 33. the path in recording mode 1 (default) dac 1st order hpf1 adc 3band eq alc (volume) dvol smute 1st order lpf stereo separation gain compensation 1st order hpf2 1 band eq mono dem figure 34. the path in playback mode 1 dac adc dvol smute 1st order hpf1 mono dem figure 35. the path in recording mode 2 & playback mode 2 1 band eq dac 1st order hpf2 adc 3 band eq alc (volume) smute 1st order lpf stereo separation gain compensation 1st order hpf1 mono dem dvol mic sensitivity correction figure 36. the path in loopback mode
[AK4950] ms1320-e-00 2011/10 - 41 - digital programmable filter circuit (1) high pass filter (hpf2) normally, this hpf is used for wind-noise reduction. this is composed 1st order hpf. the coefficient of hpf is set by 03h, 04h, 06h (3-wire mode, coew bit = ?1?) and 83h, 84h and 86h (i 2 c mode). hpf bit controls on/off of the hpf2. when the hpf2 is off, the audio data passes this block by 0db gain. the coefficient must be set when pmpfil bit = ?0?. the hpf2 starts operation 2/fs (max) after when hpf bit=pmpfil bit= ?1? is set. fs: sampling frequency fc: cutoff frequency register setting (register map 2) ( 1 note 37) a0: register addr = 03h(3-wire mode), 83h(i 2 c mode) a1: register addr = 04h(3-wire mode), 84h(i 2 c mode) b1: register addr = 06h(3-wire mode), 86h(i 2 c mode) a0 = 1 / tan ( fc /fs) 1 + 1 / tan ( fc/fs) b1 = 1 / tan ( fc/fs) ? 1 1 / tan ( fc /fs) + 1 , a1 = ? a0, transfer function h(z) = a0 1 ? z ? 1 1 ? b1 z ? 1 the cut-off frequency must be set as below. fc/fs 0.0001 (fc min = 4.41hz at 44.1khz) setting example) when fc=150hz @ fs=44.1khz (i 2 c mode) a0 = 0fd4b1 (hex): addr. 83h a1 = f02b4f (hex): addr. 84h b1 = 0fa963 (hex): addr. 86h
[AK4950] ms1320-e-00 2011/10 - 42 - (2) low pass filter (lpf) this is composed with 1st order lpf. 09h, 0ah, 0ch (3-wire mode, coew bit = ?1?) and 89h~8ah and 8ch (i 2 c mode) set the coefficient of lpf. lpf bit controls on/off of the lpf. when the lpf is off, the audio data passes this block by 0db gain. the coefficient must be set when pmpfil bit = ?0?. the lpf starts operation 2/fs (max) after when lpf bit =pmpfil bit= ?1? is set. fs: sampling frequency fc: cutoff frequency register setting (register map 2) ( 1 note 37 ) a0: register addr = 09h(3-wire mode), 89h(i 2 c mode) a1: register addr = 0ah(3-wire mode), 8ah(i 2 c mode) b1: register addr = 0ch(3-wire mode), 8ch(i 2 c mode) a0 = a1 = b1 = 1 / tan ( fc /fs) ? 1 1 / tan ( fc/fs) + 1 1 1 + 1 / tan ( fc/fs) , transfer function h(z) = a0 1 + z ? 1 1 ? b1 z ? 1 the cut-off frequency must be set as below. fc/fs 0.05 (fc min = 2205hz at 44.1khz) setting example) when fc=15khz @ fs=44.1khz (i 2 c mode) a0 = 0a53f3 (hex): addr. 89h a1 = 0a53f3 (hex): addr. 8ah b1 = fb581a (hex): addr. 8ch
[AK4950] ms1320-e-00 2011/10 - 43 - (3) stereo separation emphasis filter (fil3) fil3 is used to emphasize the stereo separation of stereo microphone recording data and playback data. address 0fh, 10h, 11h, 12h and 13h (3-wire mode, coew bit = ?1?), and address 8fh, 90h, 91h, 92h and 93h (i 2 c mode) set the filter coefficients of fil3. fil3 bit controls on/off of the fil3. when the stereo separation emphasis filter is off, the audio data passes this block by 0db gain. the coefficient s hould be set when pmpfil bit = ?0?. the fil3 starts operation 2/fs(max) after when fil3 bit =pmpfil bit= ?1? is set. 1) in case of setting fil3 as lpf fs: sampling frequency fc: cutoff frequency : gain (0.25 1) * db [db], = 10 db/20 = sin (2 fc / fs) / 2q gain =20 log (q)[db] for fs. normally q should be set to 0.7071. register setting (register map2) ( 1 note 37 ) a0: register addr = 0fh(3-wire mode), 8fh(i 2 c mode) a1: register addr = 10h(3-wire mode), 90h(i 2 c mode) a2: register addr = 11h(3-wire mode), 91h(i 2 c mode) b1: register addr = 12h(3-wire mode), 92h(i 2 c mode) b2: register addr = 13h(3-wire mode), 93h(i 2 c mode) a0 = a2 = 1? cos (2 fc/fs) 2 1 1+ a1 = 1? cos (2 fc/fs) 1+ b1 = 2 cos (2 fc/fs) 1+ b2 = +1 ?1 transfer function h x (z) = a 0 + a 1 z ? 1 + a 2 z ? 2 1 ? b 1 z ? 1 ? b 2 z ? 2 the cut-off frequency must be set as below. fc / fs < 0.497 setting example) when fc=15khz @ fs=44.1khz. (i 2 c mode) a0 = 03d96b (hex): addr. 8fh a1 = 07b2d5 (hex): addr. 90h a2 = 03d96b (hex): addr. 91h b1 = f53f37 (hex): addr. 92h b2 = fbf575 (hex): addr. 93h
[AK4950] ms1320-e-00 2011/10 - 44 - (4) gain compensation (eq0) gain compensation is used to compensate the frequency respons e and the gain that is changed by the stereo separation emphasis filter. gain compensation is composed of th e equalizer (eq0) and the gain (0db/+6db/+12db/+24db). address 19h ~ 1dh(3-wire mode, coew bit = ?1?) and address 99h~9dh (i 2 c mode) set the coefficient of eq0. gn1-0 bits set the gain ( table 26 ). eq0 bit controls on/off of eq0. when eq is off and the gain is 0db, the audio data passes this block by 0db gain. the coefficient should be set when eq0 bit = ?0? or pmpfi l bit = ?0?. the eq0 starts operation 2/fs(max) after when eq0 bit =pmpfil bit= ?1? is set. 1) when eq0 = high boost filter fs: sampling frequency fc: cutoff frequency q a / = a = boost gain. example) boost gain = +12db (a = 10 gain [db] / 40 ) when a=2. gain =20 log (q)[db] for fs. normally q should be set to 0.7071. register setting (register map 2) ( 1 note 37 ) a0: register addr = 19h(3-wire mode), 99h(i 2 c mode) a1: register addr = 1ah(3-wire mode), 9ah(i 2 c mode) a2: register addr = 1bh(3-wire mode), 9bh(i 2 c mode) b1: register addr = 1ch(3-wire mode), 9ch(i 2 c mode) b2: register addr = 1dh(3-wire mode), 9dh(i 2 c mode) a0 = ( a+1 ) ? ( a ? 1 ) cos ( 2 fc/fs ) + sin ( 2 fc/fs ) a (( a+1 ) + ( a ? 1 ) cos ( 2 fc/fs ) + sin ( 2 fc/fs )) a1 = ( a+1 ) ? ( a ? 1 ) cos ( 2 fc/fs ) + sin ( 2 fc/fs ) ? 2a (( a ? 1 ) + ( a+1 ) cos ( 2 fc/fs ) ) a2 = ( a+1 ) ? ( a ? 1 ) cos ( 2 fc/fs ) + sin ( 2 fc/fs ) a (( a+1 ) ? ( a ? 1 ) cos ( 2 fc/fs ) ? sin ( 2 fc/fs )) b1 = ( a+1 ) ? ( a ? 1 ) cos ( 2 fc/fs ) + sin ( 2 fc/fs ) ? 2 (( a ? 1 ) ? ( a+1 ) cos ( 2 fc /fs ) ) b2 = ( a+1 ) ? ( a ? 1 ) cos ( 2 fc/ fs ) + sin ( 2 fc/fs ) ( a+1 ) + ( a ? 1 ) cos ( 2 fc/fs ) ? sin ( 2 fc/fs )) ? transfer function h x (z) = a 0 + a 1 z ? 1 + a 2 z ? 2 1 ? b 1 z ? 1 ? b 2 z ? 2 the cut-off frequency must be set as below. fc 1 / fs < 0.497 gain fc frequency figure 37. eq0 frequency response (high ?boost)
[AK4950] ms1320-e-00 2011/10 - 45 - 2) when eq0 = low boost filter fs: sampling frequency fc: cutoff frequency q a / = a = boost gain. example) boost gain = +12db (a = 10 gain [db] / 40 ) when a=2. gain =20 log (q)[db] for fs. normally q should be set to 0.7071. register setting (register map 2) ( 1 note 37 ) a0: register addr = 19h(3-wire mode), 99h(i 2 c mode) a1: register addr = 1ah(3-wire mode), 9ah(i 2 c mode) a2: register addr = 1bh(3-wire mode), 9bh(i 2 c mode) b1: register addr = 1ch(3-wire mode), 9ch(i 2 c mode) b2: register addr = 1dh(3-wire mode), 9dh(i 2 c mode) a0 = ( a+1 ) + ( a ? 1 ) cos ( 2 fc/fs ) + sin ( 2 fc/fs ) a (( a+1 ) + ( a ? 1 ) cos ( 2 fc/fs ) + sin ( 2 fc/fs )) a1 = (a+1) + (a?1) cos (2 fc/fs) + sin (2 fc/fs) 2a (( a+1 ) ? ( a+1 ) cos ( 2 fc/fs ) a2 = ( a+1 ) + ( a ? 1 ) cos ( 2 fc/fs ) + sin ( 2 fc/fs ) ? a (( a+1 ) ? ( a ? 1 ) cos ( 2 fc/fs ) ? sin ( 2 fc/fs )) b1 = ( a+1 ) + ( a ? 1 ) cos ( 2 fc/fs ) + sin ( 2 fc/fs ) ? 2 (( a ? 1 ) ? ( a+1 ) cos ( 2 fc /fs ) ) b2 = ( a+1 ) + ( a ? 1 ) cos ( 2 fc/fs ) + sin ( 2 fc /fs ) ( a+1 ) + ( a ? 1 ) cos ( 2 fc/fs ) ? sin ( 2 fc /fs )) transfer function h x (z) = a 0 + a 1 z ? 1 + a 2 z ? 2 1 ? b 1 z ? 1 ? b 2 z ? 2 the cut-off frequency must be set as below. fc 1 / fs < 0.497 gain fc frequency figure 38. eq0 frequency response (low ?boost)
[AK4950] ms1320-e-00 2011/10 - 46 - gn1 bit gn0 bit gain 0 0 0db (default) 0 1 +6db 1 0 +12db 1 1 +24db table 26. gain select of the gain block setting example) gain compensation eq0: high-boost, fs=44.1khz, fc= 3.5khz, q= 0.7071 (gain =+3db) (i 2 c mode) a0 =1565f1 (hex): addr. 99h a1 =e1a168 (hex): addr. 9ah a2 = 0c79dc (hex): addr. 9bh b1 = 14fcf9 (hex): addr. 9ch b2 = f781d1 (hex): addr. 9dh (3) 3-band equalizer & 1-band equalizer after alc this block can be used as equalizer or notch filter. 3-band equalizer (eq2, eq3, and eq4) is switched on/off independently by eq2, eq3, and eq4 bits. on/off switchi ng of the equalizer after alc (eq1) is controlled by coefficients. when the equalizer is off, the audio data pa sses this block by 0db gain. address 6bh ~ 6fh (3-wire mode, coew bit = ?1?) and address ebh~efh (i 2 c mode) set the coefficient of eq1. address 20h ~ 26h(3-wire mode, coew bit = ?1?) and address a0h~a6h (i 2 c mode) set the coefficient of eq2. address 29h ~ 2fh(3-wire mode, coew bit = ?1?) and address a9h~afh (i 2 c mode) set the coefficient of eq3. address 32h ~ 36h(3-wire mode, coew bit = ?1?) and address b2~b6h (i 2 c mode) set the coefficient of eq4. the eqx (x=1, 2, 3 or 4) coefficient must be set when pmpfil bit = ?0?. eq1-4 start operation 2/fs(max) af ter when eqx (x=1, 2, 3 or 4) = pmpfil bit = ?1? is set. 1) when eq1 ~ eq4 = notch filter fs: sampling frequency fo: center frequency = sin(2 fc/fs) / 2q a = boost gain example) boost gain = +12db (a = 10 gain [db] / 40 ) when a=2 q = fo/bw (bw: band width) a0 = a2 = 1 + 1 a1 = 1 + ? 2 cos ( 2 fc/fs ) b1 = 1 + 2 cos ( 2 fc/fs ) b2 = 1+ 1? ? the cut-off frequency must be set as below. eq1, eq4: 0.0625 < fo n / fs < 0.497 eq2, eq3: fo n / fs < 0.497
[AK4950] ms1320-e-00 2011/10 - 47 - 2) when eq1 ~ eq4 = dip boost filter fs: sampling frequency fo: center furequency = sin (2 fc/fs) / 2q a = boost gain example) boost gain = +12db (a = 10 gain [db] / 40 ) when a=2. q = fo/bw (bw: band width) a0 = a + a (1+ a) a1 = a + ? 2acos ( 2 fc/fs ) a2 = a + a (1? a) b1 = a + 2acos ( 2 fc /fs ) b2 = a + a ? the cut-off frequency must be set as below. eq1, eq4: 0.0625 < fo n / fs < 0.497 eq2, eq3: fo n / fs < 0.497 setting example) eq2 (notch filter ) fs = 44.1khz, fo = 8khz, bw =200hz (i 2 c mode) a0 = 0fd201 (hex): addr. a0h a1 = f2c80f (hex): addr. a1h a2 = 0fd201 (hex): addr. a2h b1 = 0d37f1 (hex): addr. a3h, a5h b2 = f05bfe (hex): addr. a4h, a6h note 37. [translation the filter coefficient calcula ted by the equations above from real number to binary code (2?s complement)] x = (real number of filter coefficient calculated by the equations above) x 2 20 x should be rounded to integer, and then should be translated to binary code (2?s complement). msb of each filter coefficient se tting register is sine bit.
[AK4950] ms1320-e-00 2011/10 - 48 - alc operation the alc (automatic level control) is operated by alc bloc k when alc bit is ?1?. when adcpf bit is ?1?, the alc circuit operates for recording path. when adcpf bit is ?0?, the alc circuit operates for playback path. alc bit controls on/off of alc operation. note 38. in this section, vol means ivl and ivr for recording path, ovl and ovr for playback path. note 39. in this section, ref means iref for recording path, oref for playback path. 1. alc limiter operation during alc limiter operation, when either l or r channe l output level exceeds the alc limiter detection level ( table 27 ), the vol value (l/r in common) is attenuated automatically to the level under alc recovery counter reset level. the attenuate amount is depends on output level ( table 28 ). the volume is attenuated by the amount (l/r in common) shown in table 28 in every one sampling. (when alc limiter operation is executed, this attenuate operation is repeated for 16 times.) after completing the attenuate operation, unless alc bit is ch anged to ?0?, the operation repeats when the input signal level exceeds alc limiter detection level. lmth1 bit lmth0 bit alc limiter detection level (lm level) alc recovery counter reset level 0 0 ?2.5dbfs ?4.1dbfs (default) 0 1 ?4.1dbfs ?6.0dbfs 1 0 ?6.0dbfs ?8.5dbfs 1 1 ?8.5dbfs ?12dbfs table 27. alc limiter detection leve l / recovery counter reset level output level att amount [db] output level (*) >= +0.53dbfs 0.38142 ?1.16dbfs < output level < +0.53dbfs 0.06812 lm level < output level < ?1.16dbfs 0.02548 (*) compare with the next output data table 28. alc limiter att amount
[AK4950] ms1320-e-00 2011/10 - 49 - 2. alc recovery operation alc recovery operation waits for the time set by wtm1-0 bits ( table 29 ) after completing alc limiter operation. if the input signal does not exceed ?alc rec overy waiting counter reset level? ( table 27 ) during the wait time, alc recovery operation is executed. the vol value is automatically incremented by the amount set by rgain2-0 bits ( table 30 ) up to the set reference level ( table 31 ) in every one sampling. when the vol valu e exceeds the reference level (ref7-0), the vol values are not increased. when ?alc recovery waiting counter reset level (lmth1-0) output signal < alc limiter detection level (lmth1-0)? during the alc recovery operation, the waiting timer of alc recovery operation is reset. when ?alc recovery waiting counter reset level (lmth1-0) > output signal?, the waiting timer of alc recovery operation starts. alc operations correspond to the impulse noise. when the im pulse noise is input, the alc recovery operation becomes faster than a normal recovery operation. when large noise is input to a micr ophone instantaneously, the quality of small level in the large noise can be improved by this fast recove ry operation. the speed of fast recovery operation is set by rfst1-0 bits ( table 33 ). wtm1 bit wtm0 bit recovery wait time 0 0 128/fs 0 1 256/fs 1 0 512/fs 1 1 1024/fs table 29. alc recovery operation waiting period rgain2 bit rgain1 bit rgain0 bit gain amount [db] 0 0 0 0.0042 (default) 0 0 1 0.0021 0 1 0 0.0011 0 1 1 0.0005 1 0 0 0.0003 1 0 1 0.0001 1 1 0 0.00007 1 1 1 0.00003 table 30. alc recovery gain amount
[AK4950] ms1320-e-00 2011/10 - 50 - iref7-0 bits gain [db] step f0h +35.625 efh +35.25 : : e1h +30.0 (default) : : 92h +0.375 91h 0.0 90h -0.375 : : 0.375 db 2h -53.625 1h -54.0 0h mute table 31. reference level of alc recovery operation for recoding oref7-0 bits gain [db] step f0h +35.625 efh +35.25 : : e1h +30.0 (default) : : 92h +0.375 91h 0.0 90h -0.375 : : 0.375 db 2h -53.625 1h -54.0 0h mute table 32. reference level of alc recovery operation for playback rfst1-0 bits fast recovery gain amount [db] 00 0.0032 01 0.0042 10 0.0064 11 0.0127 table 33. fast recovery gain setting
[AK4950] ms1320-e-00 2011/10 - 51 - 3. the volume at alc operation the volume value during alc operation is reflected in vol7-0 bits. it is possible to check the current volume by reading the register value of vol7-0 bits. vol7-0 bits gain [db] vol7-0 bits gain [db] edh +34.5 gain +35.625 7dh ?7.5 gain < ?6.0 e9h +33.0 gain < +34.5 79h ?9.0 gain < ?7.5 e5h +31.5 gain < +33.0 75h ?10.5 gain < ?9.0 e1h +30.0 gain < +31.5 71h ?12.0 gain < ?10.5 ddh +28.5 gain < +30.0 6dh ?13.5 gain < ?12.0 d9h +27.0 gain < +28.5 69h ?15.0 gain < ?13.5 d5h +25.5 gain < +27.0 65h ?16.5 gain < ?15.0 d1h +24.0 gain < +25.5 61h ?18.0 gain < ?16.5 cdh +22.5 gain < +24.0 5dh ?19.5 gain < ?18.0 c9h +21.0 gain < +22.5 59h ?21.0 gain < ?19.5 c5h +19.5 gain < +21.0 55h ?22.5 gain < ?21.0 c1h +18 gain < +19.5 51h ?24.0 gain < ?22.5 bdh +16.5 gain < +18 4dh ?25.5 gain < ?24.0 b9h +15.0 gain < +16.5 49h ?27.0 gain < ?25.5 b5h +13.5 gain < +15.0 45h ?28.5 gain < ?27.0 b1h +12.0 gain < +13.5 41h ?30.0 gain < ?28.5 adh +10.5 gain < +12.0 3dh ?31.5 gain < ?30.0 a9h +9.0 gain < +10.5 39h ?33.0 gain < ?31.5 a5h +7.5 gain < +9.0 35h ?34.5 gain < ?33.0 a1h +6.0 gain < +7.5 31h ?36.0 gain < ?34.5 9dh +4.5 gain < +6.0 2dh ?37.5 gain < ?36.0 99h +3.0 gain < +4.5 29h ?39.0 gain < ?37.5 95h +1.5 gain < +3.0 25h ?40.5 gain < ?39.0 91h 0 gain < +1.5 21h ?42.0 gain < ?40.5 8dh ?1.5 gain < 0 19h ?45.0 gain < ?42.0 89h ?3.0 gain < ?1.5 11h ?48.0 gain < ?45.0 85h ?4.5 gain < ?3.0 01h ?54.0 gain < ?48.0 81h ?6.0 gain < ?4.5 0h mute table 34. value of vol7-0 bits
[AK4950] ms1320-e-00 2011/10 - 52 - 4. example of alc setting table 35 and table 36 show the examples of the alc setting for recording and playback path. fs=8khz fs=48khz register name comment data operation data operation lmth1-0 limiter detection level 01 ? 4.1dbfs 01 ? 4.1dbfs wtm1-0 recovery waiting period 01 32ms 11 21.3ms iref7-0 maximum gain at recovery operation e1h +30db e1h +30db ivl7-0, ivr7-0 gain of ivol e1h +30db e1h +30db rgain2-0 recovery gain 011 0.0005db 011 0.0005db rfst1-0 fast recovery gain 00 0.0032db 00 0.0032db alc alc enable 1 enable 1 enable table 35. example of the alc setting (recording) fs=8khz fs=48khz register name comment data operation data operation lmth1-0 limiter detection level 01 ? 4.1dbfs 01 ? 4.1dbfs wtm1-0 recovery waiting period 01 32ms 11 21.3ms oref7-0 maximum gain at recove ry operation a1h +6db a1h +6db ovl7-0, ovr7-0 gain of ivol 91h 0db 91h 0db rgain2-0 recovery gain 011 0.0005db 011 0.0005db rfst1-0 fast recovery gain 00 0.0032db 00 0.0032db alc alc enable 1 enable 1 enable table 36. example of the alc setting (playback)
[AK4950] ms1320-e-00 2011/10 - 53 - 5. example of registers set-up sequence of alc operation the following registers must not be changed during alc opera tion. these bits must be changed after alc operation is finished by alc bit= ?0?. the volume is changed in soft transition until the AK4950 becomes manual mode after alc bit is set to ?0?. lmth1-0, wtm1-0, rgain 2-0, ir ef7-0, oref7-0, rfst1-0 bits manual mode * the value of ivol should be the same or smaller than ref?s wr ( ivl/r 7-0) wr (iref7-0) wr (wtm 1-0, rfst1-0) example: recovery wait time = 21.3ms@48khz recovery quantity = 0.0005 db fast recovery quantity = 0.0032 db maximum gain = +30.0db limiter detection level = ? 4.1dbfs alc bit = ?1? (1) addr=20h&21h data=e1h (2) addr=24h, data=e1h (3) addr=26h, data=30h alc operation wr (rgain2-0, lmth1-0; alc = ?1?) (4) addr=27h, data=59h figure 39. registers set-up sequence at alc1 operation (recording path)
[AK4950] ms1320-e-00 2011/10 - 54 - input digital volume (manual mode) the input digital volume becomes manual mode at alc bit = ?0? when adcpf bit =?1?. this mode is used in the case shown below. 1. after exiting reset state, when setting up the registers for alc operation (lmth and etc.) 2. when the registers for alc operation (limiter pe riod, recovery period and etc.) are changed. for example; when the sampling frequency is changed. 3. when ivol is used as a manual volume control. ivl7-0 and ivr7-0 bits set the gain of the volume control ( table 37 ). when the ivol value is changed, the transition is executed via soft changes. the transiti on time between set values is 10ms@fs =44.1khz. l and r channel volumes are set individually by ivl7-0 and ivr7-0 bits when ivolc bit = ?0?. ivl7-0 bits control both l and r channel volumes together when ivolc bit = ?1?. ivl7-0 bits ivr7-0 bits gain [db] step f1h +36.0 f0h +35.625 efh +35.25 : : e2h +30.375 e1h +30.0 (default) e0h +29.625 : : 03h ? 53.25 02h ? 53.625 01h ? 54 0.375db 00h mute table 37. input digital volume setting if ivl7-0 or ivr7-0 bits are written during pmpfil bit = ?0 ?, ivol operation starts with the written values after pmpfil bit is changed to ?1?. when changing adcpf bit, the volume value is changed to ovl/r(ivl/r) from ivl/r(ovl/r). the switching noise can be reduced by setting into soft mute sate (smute bit = ?1?) before changing adcpf bit.
[AK4950] ms1320-e-00 2011/10 - 55 - output digital volume (manual mode) the alc block becomes output digital volume (manual mode) by setting alc bit to ?0? when pmpfil = pmdac bits = ?1? and adcpf bit is ?0?. the output digital volume gain is set by the ovl7-0 bit and the ovr7-0 bit ( table 38 ). when the ovolc bit = ?1?, the ovl7-0 b its control both l and r channel volume levels. when the ovolc bit = ?0?, the ovl7-0 bits control l channel volume level and the ovr7- 0 bits control r channel volume level. the volume change is executed via soft transition. the transition time between set values is 10ms@fs =44.1khz. when changing adcpf bit, the volume value is changed to ovl/r(ivl/r) from ivl/r(ovl/r). the switching noise can be reduced by setting into soft mute sate (smute bit = ?1?) before changing adcpf bit. ovl7-0 bits ovr7-0 bits gain [db] step f1h +36.0 f0h +35.625 efh +35.25 : : 92h +0.375 91h 0.0 (default) 90h -0.375 : : 0.375db 2h -53.625 1h -54.0 0h mute table 38. output digital volume setting output digital volume 2 the volume of both l and r channels are controlled t ogether by the dvl7-0. setting values are shown in table 39 . the volume change is executed via soft tran sition. it can be changed during alc operation. the transition time between set values is 10ms@fs =44.1khz. dvol7-0 bits gain [db] step f1h +18.0 f0h +17.625 efh +17.25 : : 92h +0.375 91h 0.0 (default) 90h -0.375 : : 0.375db 2h -71.625 1h -72.0 0h mute table 39. output digital volume2 setting
[AK4950] ms1320-e-00 2011/10 - 56 - digital hpf1 a digital high pass filter (hpf) is integrated for dc offset cancellation of the adc input. the cut-off frequencies of the hpf1 are set by hpfc1-0 bits ( table 40 ). it is proportional to the sampling fre quency (fs) and default is 3.4hz (@fs = 44.1khz). hpfad bit controls the on/off of the hpf1 (hpf on is recommended). fc hpfc1 bit hpfc0 bit fs=44.1khz fs=22.05khz fs=8khz 0 0 3.4hz 1.7hz 0.62hz (default) 0 1 13.6hz 6.8hz 2.47hz 1 0 108.8hz 54.4hz 19.7hz 1 1 217.6hz 108.8hz 39.5hz table 40. hpf1 cut-off frequency de-emphasis filter the AK4950 includes a digital de -emphasis filter (tc = 50/15 s) which corresponds three kinds frequency (32khz, 44khz, 48khz) by iir filter. setting the dem1 -0 bits enables the de-emphasis filter ( table 41 ). dem1 dem0 mode 0 0 44.1khz 0 1 off (default) 1 0 48khz 1 1 32khz table 41. de-emphasis control
[AK4950] ms1320-e-00 2011/10 - 57 - soft mute soft mute operation is performed in the digital domain. when the smute bit is set ?1?, the output signal is attenuated to - in 10ms@fs =44.1khz. when the smute bit is returned to ?0?, the mute is cancelled and the output attenuation gradually changes to the value set by dvol7-0 bits from - in 10ms@fs =44.1khz. if the soft mute is cancelled before attenuating to - , the attenuation is discontinued a nd the volume returns to the level set by dvol7-0 bits in the same cycle. the soft mute function is effective for changing signal source without stopping the signal transmission at playback path. smute bit is invalid during an alc operation. smute bit attenuation tbd 0db - f tbd gd gd (1) (2) (3) analog output figure 40. soft mute function (1) the input signal is attenuated to f (?0?) during 10ms@fs =44.1khz. (2) analog output corresponding to digital input has group delay (gd). (3) if soft mute is cancelled before attenuating to f , the attenuation is discounted and returned to the level set by dvol7-0 bits within the same cycle.
[AK4950] ms1320-e-00 2011/10 - 58 - stereo line output (lout, rout pin) when pmbp bit = ?0?, pmlo bit= ?1? and dacl bit is set to ?1?, l and r channel signals of dac are output in single-ended format from the lout and rout pins. when dacl bit is ?0?, output signals are muted and lout and rout pins output common voltage. the load impedance is 10k (min.). when the pmlo bit = lops bit = ?0?, the stereo line output enters power-down mode and the output is pulled-down to vss1 by 100k (typ). when the lops bit is ?1?, stereo line output enters power-sav e mode. pop noise at power-up/down can be reduced by changing pmlo bit when lops bit = ?1?. in this case, output signal line should be pulled-down by 20k after ac coupled as figure 42 . rise/fall time is 300ms (max) if c=1 f and r l =10k . when pmlo bit = ?1? and lops bit = ?0?, stereo line output is in normal operation. lovl1-0 bits set the gain of stereo line output. dac ?dacl bit? lout pin rout pin ?lovl1-0 bits? figure 41. stereo line output lops pmlo mode lout/rout pin 0 power down pull-down to vss1 (default) 0 1 normal operation normal operation 0 power save fall down to vss1 1 1 power save rise up to common voltage table 42. stereo line output mode select lovl1-0 bits avdd gain 00 2.7 ~ 3.6 v 0db 01 3.0 ~ 3.6 v +1.34db (default) 10 2.7 ~ 3.6 v +2db 11 3.0 ~ 3.6 v +3.34db table 43. stereo lineout volume setting lout rout 1 f 220 20k figure 42. external circuit for stereo line output (in case of using a pop noise reduction circuit)
[AK4950] ms1320-e-00 2011/10 - 59 - [stereo line output control sequence (in case of using a pop noise reduction circuit)] pmlo bit lops bit lout, rout pins (1) (2) normal output (3) (4) (5) (6) 300 ms 300 ms 99% common voltage 1% common voltage figure 43. stereo line output control sequence (in case of using a pop noise reduction circuit) (1) set lops bit = ?1?. stereo line out put enters the power-save mode. (2) set pmlo bit = ?1?. stereo line output exits the power-down mode. lout and rout pins rise up to common voltage. rise time is 200ms (max 300ms) when c=1 f. (3) set lops bit = ?0? after lout and rout pins rise up. stereo line output exits the power-save mode. stereo line output is enabled. (4) set lops bit = ?1?. stereo line output enters power-save mode. (5) set pmlo bit = ?0?. stereo line output enters power-down mode. lout and rout pins fall down to 1% of the common voltage. fall time is 200ms (max 300ms) at c=1 f. (6) set lops bit = ?0? after lout and rout pins fall down. stereo line output exits the power-save mode. < mono mixing output > mono mixing outputs are availabl e by setting mono1-0 bits. input data from the sdti pin can be converted to mono signal [(l+r)/2] and are output via lout and rout pins. ( figure 32 ) mono1 bit mono0 bit lout pin rout pin 0 0 lch rch (default) 0 1 lch lch 1 0 rch rch 1 1 (lch+rch)/2 (lch+rch)/2 table 44. lout/rout pin output data switch
[AK4950] ms1320-e-00 2011/10 - 60 - line sharing of mic input and stereo lineout in external circuit (lin1/rin1, lout/rout pin) the lin1 (or rin1) pin and the lout (or rout) pin of the AK4950 can share a line in external circuit. when using the lin1(or rin1) pin as adc input, the lout(or rout) pin is pulled up (typ. 200k ) to typ. 1.35v* by setting pmadc= lops= extc bits= ?1?. when using the lout (or rout) pin as dac output, the lin1 (or rin1) pin is pulled up (typ. 100k ) to typ. 1.35v* by setting pmadc=lops bits = ?0? and extc bit = ?1?. pmadc bit lops bit (pmlo bit = ?1?) extc bit lin1/rin1 pins lout/rout pins figure 1 1 1 normal operation pull-up to typ. 1.35v (*) by 200k (typ) figure 44 1 0 1 normal operation normal operation - 0 1 1 pull-up to typ. 1.35v (*) by 100k (typ) pull-up tor typ. 1.35v (*) by 200k (typ) - 0 0 1 pull-up to typ. 1.35v (*) by 100k (typ) normal operation figure 45 x x 0 can not share a line - table 45. lin1/rin1 and lout/rout mode setting (x: don?t care) * when lovl0 bit = ?0?. 1.43v (typ) if the lovl0 bit = ?1? dac adc line out -amp avdd lout(rout) pin avdd lin1(rin1) pin t y p 100k t yp 200k from jack of apprication 1.35v(*) 1.35v(*) figure 44. lin1/rin1 : adc path: external line share (pmadc = lops = extc bits = ?1?) * when lovl0 bit = ?0?. 1.43v (typ) if the lovl0 bit = ?1?
[AK4950] ms1320-e-00 2011/10 - 61 - dac adc line out -amp avdd lout(rout) pin avdd lin1(rin1) pin t y p 100k t yp 200k from jack of apprication 1.35v(*) 1.35v(*) figure 45. dac lout/rout path: external line share (pmadc = lops bits = ?0?, extc bits = ?1?) * when lovl0 bit = ?0?. 1.43v (typ) if the lovl0 bit = ?1? v rch line output and analog mix mono input modes select when pmbp bit = ?0?, the rout/min pin outputs right channel signal of dac (rout pin mode). when pmbp bit = ?1?, the rout/min pin becomes mono input pin (min pin mode). pmlo bit pmbp bit rout/min pin mode 1 0 rout pin mode (default) x 1 min pin mode * min pin mode when pmlo = pmbp bits = ?1? table 46. rout/min pin mode select (x: don?t care) during pmbp bit = ?1?, the speak er amplifier outputs input data of the min pi n by setting beeps bit to ?1?. the lineout amplifier outputs input signal of the min pi n by setting beepl bit to ?1?. when bp m bit = ?1?, ri can control the beep signal gain which is in inverse proportion to ri resister value. table 48 and table 49 show the typical gain when r i = 66k . the external r i resister is not needed when bpm bit = ?0?. the total gain is dependent on min-amp gain which is set by bplvl2-0 bits, speaker amplifier gain (spkg1-0 bits) and stereo lineout amplifier gain (lovl1-0 bits). bpm bit beep mode 1 external resistance mode 0 internal resistance mode (default) table 47. beep mode setting
[AK4950] ms1320-e-00 2011/10 - 62 - 1. external resistance mode (bpm bit = ?1?) rout/min pin ri dac rch lineout-am p pmbp bit = ?1? lout pin beepl spp/spn pin beeps min-amp bpm bit = ?1? figure 46. block diagram of min pin (pmbp bit = ?1?, bpm bit =?1?) lovl1-0 bits min ? lout 00 0db (default) 01 +1.34db 10 +2db 11 +3.34db table 48. min ? lout output gain min ? spp/spn spkg1-0 bits alc bit = ?0? alc bit = ?1? 00 +6.1db +8.1db (default) 01 +8.1db +10.1db 10 +10.1db +12.1db 11 +12.1db +14.1db table 49. min ? spk output gain
[AK4950] ms1320-e-00 2011/10 - 63 - 2. internal resistance mode (bpm bit = ?0?) bplvl2 bplvl1 bplvl0 beep gain 0 0 0 0db (default) 0 0 1 ?6db 0 1 0 ?12db 0 1 1 ?24db 1 0 0 ?28db 1 0 1 ?32db 1 1 0 ?36db 1 1 1 ?40db table 50. beep output gain setting when bpm bit = ?0? rout/min pin dac rch lineout-am p pmbp bit = ?1? lout pin beepl spp/spn pin beeps min-amp bpm bit = ?0? figure 47. block diagram of min pin (pmbp bit = ?1?, bpm bit =?0?)
[AK4950] ms1320-e-00 2011/10 - 64 - speaker output the dac output signal is input to the speaker amplifier as mono signal [(l+r)/2]. the speaker amplifier has mono output as it is blt (bridged transless) capable. the gain and output level are set by spkg1-0 bits. the output level is depends on avdd and spkg1-0 bits setting. gain spkg1-0 bits alc bit = ?0? alc bit = ?1? 00 +6.1db +8.1db (default) 01 +8.1db +10.1db 10 +10.1db +12.1db 11 +12.1db +14.1db table 51. spk-amp gain spk-amp output (dac input=0dbfs, avdd= 3.3v) spkg1-0 bits alc bit = ?0? alc bit = ?1? (lmth1-0 bits = ?00?) 00 3.37vpp 3.17vpp (default) 01 4.23vpp ( note 40 ) 4.00vpp 10 5.33vpp ( note 40 ) 5.04vpp ( note 40 ) 11 6.71vpp ( note 40 ) 6.33vpp ( note 40 ) note 40. the output level is calculated on the assumption that the signal is not clipped. however, in the actual case, the spk-amp output signal is clipped when dac outputs 0dbfs signal. the spk-amp output level should be kept under 4.0vpp (avdd=3.3v) by adjusting digital volume to prevent clipped noise. table 52. spk-amp output level
[AK4950] ms1320-e-00 2011/10 - 65 - < speaker-amp control sequence > the speaker amplifier is powered-up/down by pmspk bit. when pmspk bit is ?0 ?, both spp and spn pins are in hi-z state. when pmspk bit is ?1? and sppsn b it is ?0?, the speaker amp lifier enters power-save mode. in this mode, the spp pin is placed in hi-z state a nd the spn pin outputs avdd/2 voltage. when the pmspk bit is ?1? after the pdn pin is changed fro m ?l? to ?h?, the spp and spn pins rise up in power-save mode. in this mode, the spp pin is placed in a hi-z stat e and the spn pin goes to avdd/2 voltage. because the spp and spn pins rise up in power-save mode, pop noise can be reduced. when the AK4950 is powered-down (pmspk bit = ?0?), pop noise can also be reduced by first entering power-save-mode. pmspk sppsn mode spp spn 0 x power-down hi-z hi-z (default) 0 power-save hi-z avdd/2 1 1 normal operation normal operation normal operation table 53 speaker-amp mode setting (x: don?t care) pmspk bit sppsn bit spp pin spn pin avdd/2 avdd/2 hi-z hi-z hi-z hi-z >1ms figure 48. power-up/power-down timing for speaker-amp thermal shutdown function when the internal temperature of the device rises up irregularly (e.g. when output pins are shortened.), the speaker amplifier is automatically powered down and then thd et bit becomes ?1?(thermal s hutdown). when the thermal shutdown is executed, the speaker amplifier, lineout amplifier, charge pump and video block are powered-down (pmspk=pmlo=pmcp=pmv bits = ?1? ?0?). writing ?1? to these registers can put each circuit in normal operation, but it may be powered down again (?1? ?0?) if the internal temperature of the device is still high. the device status can be monitored on thdet bit.
[AK4950] ms1320-e-00 2011/10 - 66 - video block the integrated cap-less video amplifier with charge pump has drivability for a load resistance of 150 ( figure 49 ). the AK4950 has a composite input a nd output. a low pass filter (lpf) and gain control amp are integrated, and vg1-0 bits set the gain (+6/+9/+12/16.5 db) ( table 54 ). the video signals can be output as pedestal level 0v by supplying negative power to the video amplifier from the charge pump circuit ( figure 50 ). therefore ac-coupling capacitor is not needed. and also, the external flying capacitor for charge pump is not needed because it is included. the video amplifier power management is controlled by pmv bit. the charge pum p circuit power management is controlled by pmcp bit. when pmv bit = ?0?, the vout pin outputs 0v. the video inputs must be ac-coupled by a 0.1 f capacitor. the video signal source impedance at transmitting side must not over 600 . vin clamp lpf vout clock generator vss4 pvee pmcp bit charge pump pmv bit +6/+9/+12/+16.5db typ 0.1f max 600 2.2f figure 49. video block diagram vg1-0 bits gain 00 +6db (default) 01 +9db 10 +12db 11 +16.5db table 54. video signal gain setting
[AK4950] ms1320-e-00 2011/10 - 67 - vout 75 a k4950 0v 75 figure 50. video signal output regulator block the AK4950 integrates two regulators. the 3.3v (typ) power supply voltage from the avdd pin is converted to 2.3v (typ) by the regulator 1 and supplied to the analog logic (mic-amp, adc, dac, min, video-amp input stage, lpf of video block and charge pump). it is also converted to 1.8v (t yp) by the regulator 2 and supplied to the digital logic (digital core block). each regulator is powered up by the pdn pin = ?h?, and powered down by the pdn pin = ?l?. connect a 2.2f ( 50%) capacitor to the regfil1 pin and a 1.0f ( 50%) capacitor to the regfil2 pin to reduce noise on avdd. AK4950 avdd to analog block regulator1 typ 2.3v regfil1 2.2 f 50% regulator2 typ 1.8v regfil2 1.0 f 50% to digital block power-up when pdn pin =?h? power-down when pdn pin =?l? figure 51 regulator block
[AK4950] ms1320-e-00 2011/10 - 68 - serial control interface (1) 3-wire mode internal registers may be written by using 3-wire mode interface pins (csn , cclk and cdtio). the data on this interface consists of read/write, register address (msb first, 7bits ) and control or output da ta (msb first, 24bits). address and data is clocked in on the rising edge of cclk and data is clocked out on the falling edge. data writings become available on the rising edge of csn. when reading the data, the cdtio pin changes to output mode at the falling edge of 8th cclk and outputs data in d 23-d0. however this reading function is available only when read bit = ?1?. when read bit = ?0?, the cdtio pin stays as hi-z even after the falling edge of 8th cclk. the data output finishes on the risi ng edge of csn. the cdtio is placed in a hi-z state except when outpu tting the data at read operation mode. clock speed of cclk is 5mhz (max). the value of internal registers are initialized by the pdn pin = ?l?. the registers on the address after 20h ar e for cram of the dsp. writing data is automatically stored in cram when coew bit is ?1? ( figure 53 ). in this case, pmpfil bit should be set to ?0?. read commands are not valid. note 41. data reading is only available on the following addresses; 00 ~ 0fh and 20h ~ 2fh. when reading the other addresses, the register values are invalid. (1)-1. when accessing to the address 00h ~ 2fh (coew bit = ?0?) csn cclk cdti a6 a5 a2 a3 a1 a0 a4 d23 d22 d21 d20 d19 d18 d17 d16 h a6-a0: register address d23-d0: control data (input) at write command (write only) ?h? or ?l? ?h? or ?l? ?h? o r ?l ? ?h? or ?l? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 d14 d13 d10 d11 d9 d8 d12 d7 d6 d5 d4 d3 d2 d1 d 0 d 15 csn cclk cdti figure 52. 3-wire mode control interface timing (coew bit = ?0?)
[AK4950] ms1320-e-00 2011/10 - 69 - (1)-2. when accessing to filter co efficients (coew bit = ?1?) csn cclk cdti a6 a5 a2 a3 a1 a0 a4 d23 d22 d21 d20 d19 d18 d17 d16 l a6-a0: register address d23-d0: control data (input) at write command (write only) ?h? or ?l? ?h? or ?l? ?h? or ?l? ?h? or ?l? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 d14 d13 d10 d11 d9 d8 d12 d7 d6 d5 d4 d3 d2 d1 d0 d15 csn cclk cdti figure 53. 3-wire mode control interface timing (coew bit = ?1?)
[AK4950] ms1320-e-00 2011/10 - 70 - (2) i2c-bus control mode (i2c pin = ?h?) the AK4950 supports the fast-mode i 2 c-bus (max: 400khz). pull-up resistors at the sda and scl pins must be connected to (tvdd+0.3)v or less voltage. (2)-1. write operations figure 54 shows the data transfer sequence for the i 2 c-bus mode. all commands are pr eceded by a start condition. a high to low transition on the sda line while scl is high indicates a start condition ( figure 62 ). after the start condition, a slave address is sent. this address is 7 bits long followed by the eighth bit that is a data direction bit (r/w). the most significant six bits of the slave address are fixed as ?001001?. the next bit is cad0 (device address bit). this bit identifies the specific device on the bus. the hard-wired input pin (cad0 pin) sets these device address bits ( figure 56 ). if the slave address matches that of the AK4950, the AK4950 generates an acknowledge and the operation is executed. the master must generate the acknowledge-relate d clock pulse and release the sda line (high) during the acknowledge clock pulse ( figure 63 ). a r/w bit value of ?1? indicates that th e read operation is to be executed, and ?0? indicates that the write operation is to be executed. the second byte consists of the control register address of the AK4950 and the format is msb first. ( figure 57 ). the data after the second byte contains control data. the format is msb first, 8bits ( figure 58 ). the AK4950 generates an acknowledge after each byte is received. data transfer is alwa ys terminated by a stop cond ition generated by the master. a low to high transition on the sda line while scl is high defines a stop condition ( figure 62 ). the AK4950 can perform more than one by te write operation per sequence. after receipt of the third byte the AK4950 generates an acknowledge and awaits the next data. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. afte r receiving each data packet the internal address counter is incremented by one, and the next data is automatically taken into the next addr ess. if the address exceeds 2fh prior to generating a stop condition, the address counter will ?roll over? to 00h and th e previous data will be overwritten. the data on the sda line must remain stable during the high period of the clock. high or low state of the data line can only be changed when the clock signal on the scl line is low ( figure 64 ) except for the start and stop conditions. the data length is different (8bit or 24bit) depending on the data address. address data length 00h ~ 2fh 8bit 80h ~ ffh 24bit table 55. data length in i 2 c-bus mode sda slave address s s t a r t r/w="0" a c k sub address(n) a c k data(n) a c k data(n+1) a c k a c k data(n+x) a c k p s t o p figure 54. data transfer sequence at i 2 c bus mode (00h ~ 2fh)
[AK4950] ms1320-e-00 2011/10 - 71 - sda slave address s s t a r t r/w="0" a c k sub address(n) a c k data(n) d23 ~ d16 a c k a c k a c k data(n+1) d23 ~ d16 p s t o p data(n) d15 ~ d8 data(n) d7 ~ d0 data(n+x) d7 ~ d0 a c k a c k a c k figure 55. data transfer sequence at i 2 c bus mode (80h ~ feh) 0 0 1 0 0 1 cad0 r/w figure 56. the first byte a7 a6 a5 a4 a3 a2 a1 a0 figure 57. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 58. the third byte (00h ~ 2fh) d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 figure 59. the third byte (80h ~ feh)
[AK4950] ms1320-e-00 2011/10 - 72 - (2)-2. read operations set the r/w bit = ?1? for the read operation of the AK4950. after transmission of data, the master can read the next address?s data by generating an acknowledge instead of terminating the write cy cle after the receipt of the first data word. after receiving each data packet the intern al address counter is incremented by one , and the next data is automatically taken into the next address. if the address exceeds 2fh prio r to generating stop condition, the address counter will ?roll over? to 00h and the data of 00h will be read out. the AK4950 supports two basic read operations: current address read and random address read. however, the AK4950 only supports random address read in dsp mode. (2)-2-1. current address read the AK4950 has an internal address counter that maintains the address of the last accessed word incremented by one. therefore, if the last access (either a read or write) were to address ?n?, the next current read operation would access data from the address ?n+1?. after receipt of the slave address with r/w bit ?1?, the AK4950 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. if the master does not generate an acknow ledge but generates a stop condition instead, the AK4950 ceases the transmission. sda slave address s s t a r t r/w="1" a c k a c k data(n+1) a c k data(n+2) a c k a c k data(n+x) n a c k p s t o p data(n) m a s t e r m a s t e r m a s t e r m a s t e r m a s t e r figure 60. current address read (2)-2-2. random address read the random read operation allows the master to access any memo ry location at random. prior to issuing the slave address with the r/w bit ?1?, the master must first perform a ?dummy? write operation. th e master issues a start request, a slave address (r/w bit = ?0?) and then the register address to read. after the register address is acknowledged, the master immediately reissues the start request and the slave addr ess with the r/w bit ?1?. the AK4950 then generates an acknowledge, 1 byte of data and increments the internal a ddress counter by 1. if the master does not generate an acknowledge but generates a stop condition instead, the AK4950 ceases the transmission. sda slave address s s t a r t r/w="0" a c k a c k a c k data(n) a c k data(n+x) a c k p s t o p sub address(n) s slave address r/w="1" s t a r t data(n+1) a c k n a c k m a s t e r m a s t e r m a s t e r m a s t e r figure 61. random address read
[AK4950] ms1320-e-00 2011/10 - 73 - scl sda stop condition start condition s p figure 62. start condition and stop condition scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 63. acknowledge (i 2 c bus) scl sda data line stable; data valid change of data allowed figure 64. bit transfer (i 2 c bus)
[AK4950] ms1320-e-00 2011/10 - 74 - register map 1 addr register name d23 d22 d21 d20 d19 d18 d17 d16 00h power management 1 pmpfil 0 pmbp pmspk pmlo pmdac pmadr pmadl 01h power management 2 adrst 0 0 0 m/s pmmp mcko pmpll 02h mic gain control 1 0 0 0 0 mgain3 m gain2 mgain1 mgain0 03h gain control micl 0 sppkg1 spkg0 0 0 lovl1 lovl0 04h mode control 1 sppsn lops 0 0 beeps beepl dacs dacl 05h mode control 2 read mlout 0 0 0 0 inr inl 06h mode control 3 0 0 extc 0 mono1 mono0 dem1 dem0 07h pll control 1 pll3 pll2 pll1 pll0 bcko 0 dif1 dif0 08h pll control 2 ps1 ps0 0 0 fs3 fs2 fs1 fs0 09h digital mic 0 0 pmdmr pmdml 0 dclke dclkp dmic 0ah beep control bpm 0 0 bpvcm 0 bplvl2 bplvl1 bplvl0 0bh hpf control 0 0 0 0 0 hpfc1 hpfc0 hpfad 0ch video control 0 0 0 0 vg1 vg0 pmcp pmv 0dh mode control 4 thdet 0 0 0 0 0 0 coew 0eh mode control 5 0 0 0 0 0 0 0 init 0fh alc level vol7 vol6 vol 5 vol4 vol3 vol2 vol1 vol0 10h reserved 0 0 0 0 0 0 0 0 11h reserved 0 0 0 0 0 0 0 0 12h reserved 0 0 0 0 0 0 0 0 13h reserved 0 0 0 0 0 0 0 0 14h reserved 0 0 0 0 0 0 0 0 15h reserved 0 0 0 0 0 0 0 0 16h reserved 0 0 0 0 0 0 0 0 17h reserved 0 0 0 0 0 0 0 0 18h reserved 0 0 0 0 0 0 0 0 19h reserved 0 0 0 0 0 0 0 0 1ah reserved 0 0 0 0 0 0 0 0 1bh reserved 0 0 0 0 0 0 0 0 1ch reserved 0 0 0 0 0 0 0 0 1dh reserved 0 0 0 0 0 0 0 0 1eh reserved 0 0 0 0 0 0 0 0 1fh reserved 0 0 0 0 0 0 0 0 20h lch input volume control ivl7 ivl6 ivl5 ivl4 ivl3 ivl2 ivl1 ivl0 21h rch input volume control ivr7 ivr6 ivr5 ivr4 ivr3 ivr2 ivr1 ivr0 22h lch output volume control ovl7 ovl6 ovl5 ovl4 ovl3 ovl2 ovl1 ovl0 23h rch output volume control ovr7 ovr6 ovr5 ovr4 ovr3 ovr2 ovr1 ovr0 24h alc mode contorl 1 iref7 iref6 iref5 iref4 iref3 iref2 iref1 iref0 25h alc mode contorl 2 oref7 oref6 oref5 oref4 oref3 oref2 oref1 oref0 26h alc mode contorl 3 0 0 wtm1 wtm0 0 0 rfst1 rfst0 27h alc mode contorl 4 smute alc rgain2 rgain1 rgain0 0 lmth1 lmth0 28h reserved 0 0 0 0 0 0 0 0 29h reserved 0 0 0 0 0 0 0 0 2ah digital volume control dvol 7 dvol6 dvol5 dvol4 dvol 3 dvol2 dvol1 dvol0 2bh mic gain control 2 msgainr3 msgainr2 msgainr 1 msgainr0 msgainl3 msgai nl2 msgainl1 msgainl0 2ch digital filter contorl 1 0 0 0 pfsdo pfdac adcpf ovolc ivolc 2dh digital filter contorl 2 0 0 lpf hpf eq0 gn1 gn0 fil3 2eh digital filter contorl 3 0 0 0 0 eq4 eq3 eq2 0 2fh reserved 0 0 0 0 0 0 0 0 note 42. pdn pin = ?l? resets the registers to their default values. note 43. the bits defined as 0 must contain a ?0? value. note 44. address 0fh is a read only register. writing access to 0fh is ignored and does not effect the operation. note 45. d15~d0 registers must contain ?0? value.
[AK4950] ms1320-e-00 2011/10 - 75 - register map 2: filter coefficient (coew bit = ?1?) control register addr i 2 c pin =?l? (3-wire mode) i 2 c pin =?h? (i 2 c mode) register name initial 01h 81h lch input volume 100000h 02h 82h rch input volume 100000h 03h 83h hpf a0 100000h 04h 84h hpf a1 000000h 06h 86h hpf b1 000000h 09h 89h lpf a0 100000h 0ah 8ah lpf a1 000000h 0ch 8ch lpf b1 000000h 0fh 8fh stereo filter a0 100000h 10h 90h stereo filter a1 000000h 11h 91h stereo filter a2 000000h 12h 92h stereo filter b1 000000h 13h 93h stereo filter b2 000000h 19h 99h eq0 a0 100000h 1ah 9ah eq0 a1 000000h 1bh 9bh eq0 a2 000000h 1ch 9ch eq0 b1 000000h 1dh 9dh eq0 b2 000000h 20h a0h eq2 a0 100000h 21h a1h eq2 a1 000000h 22h a2h eq2 a2 000000h 23h a3h eq2 b1 000000h 24h a4h eq2 b2 000000h 25h a5h eq2 b1 000000h 26h a6h eq2 b2 000000h 29h a9h eq3 a0 100000h 2ah aah eq3 a1 000000h 2bh abh eq3 a2 000000h 2ch ach eq3 b1 000000h 2dh adh eq3 b2 000000h 2eh aeh eq3 b1 000000h 2fh afh eq3 b2 000000h 32h b2h eq4 a0 100000h 33h b3h eq4 a1 000000h 34h b4h eq4 a2 000000h 35h b5h eq4 b1 000000h 36h b6h eq4 b2 000000h 6bh ebh eq1 a0 100000h 6ch ech eq1 a1 000000h 6dh edh eq1 a2 000000h 6eh eeh eq1 b1 000000h 6fh efh eq1 b2 000000h
[AK4950] ms1320-e-00 2011/10 - 76 - register definitions addr register name d23 d22 d21 d20 d19 d18 d17 d16 00h power management 1 pmpfil 0 pmbp pmspk pmlo pmdac pmadr pmadl r/w r/w r r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 pmadl: mic-amp lch and adc lch power management 0: power-down (default) 1: power-up pmadr: mic-amp rch, adc rch power management 0: power down (default) 1: power up when the pmadl or pmadr bit is changed from ?0 ? to ?1?, the initialization cycle (1059/fs=24ms @44.1khz, adrst bit = ?0?) starts. after initializing, digital data of the adc is output. pmdac: dac power management 0: power-down (default) 1: power-up pmlo: stereo line output power management 0: power-down (default) 1: power-up pmspk: speaker-amp power management 0: power-down (default) 1: power-up pmbp: mono input power management 0: power-down (default) 1: power-up the rout/min pin performs as min pin. beepl and b eeps bits control the path settings of rch lineout and speaker from the min pin respectively. pmpfil: programmable filter block (hpf2/lpf/fil3/eq/5 band eq/alc) power management (dsp system reset) 0: power down (default) 1: power up all blocks except regulators can be powered-down by writing ?0? to the address ?00h?, pmpll, pmmp, pmdml, pmdmr, dmpe, pmadr, pmv, pmcp and mcko bits. in this case, register values are maintained.
[AK4950] ms1320-e-00 2011/10 - 77 - addr register name d23 d22 d21 d20 d19 d18 d17 d16 01h power management 2 adrst 0 0 0 m/s pmmp mcko pmpll r/w r/w r r r r/ w r/w r/w r/w default 0 0 0 0 0 0 0 0 pmpll: pll power management 0: ext mode and power down (default) 1: pll mode and power up mcko: master clock output enable 0: disable: mcko pin = ?l? (default) 1: enable: output frequency is selected by ps1-0 bits. pmmp: mic power management 0: power down (default) 1: power up m/s: master / slave mode select 0: slave mode (default) 1: master mode adrst: adc initializing cycle select 0: 1059/fs (default) 1: 267/fs addr register name d23 d22 d21 d20 d19 d18 d17 d16 02h mic gain control 1 0 0 0 0 mgain3 mgain2 mgain1 mgain0 r/w r r r r r/w r/w r/w r/w default 0 0 0 0 0 1 1 0 mgain3-0: mic-amp gain control ( table 21 ) addr register name d23 d22 d21 d20 d19 d18 d17 d16 03h gain control micl 0 spkg1 spkg0 0 0 lovl1 lovl0 r/w r/w r r/w r/ w r r r/w r/w default 0 0 0 0 0 0 0 1 lovl1-0: stereo line output gain and signal ground setting ( table 43 ) spkg1-0: speaker-amp output gain select ( table 51 ) micl: mic power output voltage select 0: typ 2.5v (avdd=3.0 ~ 3.6v) (default) 1: typ 2.2v (avdd = 2.7 ~ 3.6v)
[AK4950] ms1320-e-00 2011/10 - 78 - addr register name d23 d22 d21 d20 d19 d18 d17 d16 04h mode control 1 sppsn lops 0 0 beeps beepl dacs dacl r/w r/w r/w r r r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 dacl: dac output signal to stereo line amp control 0: off (default) 1: on when pmlo bit = ?1?, this bit setting is enabled. lout and rout pins output vss1 when pmlo bit = ?0?. dacs: signal switch control from dac to speaker-amp 0: off (default) 1: on when dacs bit is ?1?, dac output signal is input to speaker-amp. beepl: signal switch control from the min pin to lineout 0: off (default) 1: on this setting is valid when pmbp bit = ?1?. set beep signal input mode by bpm bit. the signal from the min pin is input to lineout by beepl bit = ?1?. beeps: signal switch control from the min pin to speaker-amp 0: off (default) 1: on this setting is valid when pmbp bit = ?1?. set beep signal input mode by bpm bit. the signal from the min pin is input to lineout by beeps bit = ?1?. lops: stereo line output power save 0: normal operation (default) 1: power save mode sppsn: speaker-amp power-save mode 0: power-save mode (default) 1: normal operation when sppsn bit is ?0?, speaker-amp is in power-save mode. in this mode, the spp pin goes to hi-z and the spn pin outputs avdd/2 voltage. when pmspk bit = ?1?, sppsn bit is enabled. after the pdn pin is set to ?l?, speaker-amp is in power-dow n mode since pmspk bit is ?0?. addr register name d23 d22 d21 d20 d19 d18 d17 d16 05h mode control 2 read mlout 0 0 0 0 inr inl r/w r/w r/w r r r r r/w r/w default 0 0 0 0 0 0 0 0 inl: adc lch input source select 0: lin1 pin (default) 1: lin2 pin inr: adc rch input source select 0: rin1 pin (default) 1: rin2 pin
[AK4950] ms1320-e-00 2011/10 - 79 - mlout: lineout mono mode switch 0: lineout stereo mode (default) both l and r channel lineout amplifiers are powered-up when pmlo bit = ?0?. 1: lineout mono mode only l channel lineout amplifier is powered-up when pmlo bit = ?1?. r channel lineout amplifier is powered-down. read: read function enable 0: disable (default) 1: enable addr register name d23 d22 d21 d20 d19 d18 d17 d16 06h mode control 3 0 0 extc 0 mono1 mono0 dem1 dem0 r/w r r r/w r r/w r/w r/w r/w default 0 0 0 0 0 0 0 1 dem1-0: de-emphasis control ( table 41 ) default: ?01? (off) mono1-0: lout/rout output signal mode select ( table 44 ) extc: lin1/rin1 and lout/rout external connect mode switch ( table 45 ) 0: external connect mode disable (default) 1: external connect mode enable addr register name d23 d22 d21 d20 d19 d18 d17 d16 07h pll control 1 pll3 pll2 pll1 pll0 bcko 0 dif1 dif0 r/w r/w r/w r/w r/ w r/w r r/w r/w default 0 1 1 0 0 0 1 0 dif1-0: audio interface format ( table 17 ) default: ?10? (msb justified) bcko: master mode bick output frequency setting ( table 10 ) pll3-0: pll reference clock select ( table 4 ) default: ?0110? (mcki pin, 12mhz) addr register name d23 d22 d21 d20 d19 d18 d17 d16 08h pll control 2 ps1 ps0 0 0 fs3 fs2 fs1 fs0 r/w r/w r/w r r r/w r/w r/w r/w default 0 0 0 0 1 1 1 1 fs3-0: sampling frequency ( table 5 , table 6 ) and mcki frequency ( table 11 ) setting these bits control sampling frequency in pll mode and control mcki input frequency in ext mode. ps1-0: mcko frequency setting ( table 9 ) default: ?00? (256fs)
[AK4950] ms1320-e-00 2011/10 - 80 - addr register name d23 d22 d21 d20 d19 d18 d17 d16 09h digital mic 0 0 pmdmr pmdml 0 dclke dclkp dmic r/w r r r/w r/w r r/w r/w r/w default 0 0 0 0 0 0 0 0 dmic: digital microphone connection select 0: analog microphone (default) 1: digital microphone dclkp: data latching edge select 0: lch data is latched on the dmclk rising edge (? ?). (default) 1: lch data is latched on the dmclk falling edge (? ?). dclke: dmclk pin output clock control 0: ?l? output (default) 1: 64fs output pmdml/r: input signal select with digital microphone ( table 19 ) default: ?00? adc digital block is powered-down by pmdml = pmdmr bits = ?0? when selecting a digital microphone input (dmic bit = ?1?, inl/r bits = ?00?, ?01? or ?10?). addr register name d23 d22 d21 d20 d19 d18 d17 d16 0ah beep control bpm 0 0 bpvcm 0 bplvl2 bplvl1 bplvl0 r/w r/w r r r/w r r/w r/w r/w default 0 0 0 0 0 0 0 0 bplvl2-0: beep output level setting ( table 50 ) default: ?0h?: 0db bpvcm: common voltage setting of min input amplifier 0: 1.15v (default) 1: 1.65v bpm: beep mode setting ( table 47 ) default: ?0?: internal resistance mode
[AK4950] ms1320-e-00 2011/10 - 81 - addr register name d23 d22 d21 d20 d19 d18 d17 d16 0bh hpf control 0 0 0 0 0 hpfc1 hpfc0 hpfad r/w r r r r r r/w r/w r/w default 0 0 0 0 0 0 0 1 hpfad: hpf1 control of adc 0: off 1: on (default) when hpfad bit is ?1?, the settings of hpfc1-0 bits are enabled. when hpfad bit is ?0?, hpfad block is through (0db). when pmadl bit = ?1? or pmadr b it = ?1?, set hpfad bit to ?1?. hpfc1-0: cut-off frequency setting of hpf1 (adc) ( table 40 ) default: ?00? (3.4hz @ fs = 44.1khz) addr register name d23 d22 d21 d20 d19 d18 d17 d16 0ch video control 0 0 0 0 vg1 vg0 pmcp pmv r/w r r r r r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 pmv: composite video block power management (vin pin vout pin) 0: power down (default) 1: power up pmcp: charge pump power management 0: power down (default) 1: power up vg1-0: video amp gain select vg1-0 bits gain(db) 00 +6db (default) 01 +9db 10 +12db 11 +16.5db table 54. video signal gain setting
[AK4950] ms1320-e-00 2011/10 - 82 - addr register name d23 d22 d21 d20 d19 d18 d17 d16 0dh mode control 4 thdet 0 0 0 0 0 0 coew r/w r r r r r r r r/w default 0 0 0 0 0 0 0 0 coew: filter coefficient write enable 0: disable (default) 1: enable thdet: thermal shutdown detection (read only) this bit becomes ?1? when the internal temperature of lsi exceeds 170c (typ). when thdet bit changes to ?1?, pmspk, pmlo, pmv and pmcp bits become ?0? forc ibly. thdet bit returns to ?0? when the internal temperature is down, however, pmspk, pmlo , pmv and pmcp bits stays ?0?. addr register name d23 d22 d21 d20 d19 d18 d17 d16 0eh mode control 5 0 0 0 0 0 0 0 init r/w r r r r r r r r/w default 0 0 0 0 0 0 0 0 init: programmable filter initializing programmable filter coefficients are initialized by init bit = ?1?. init bit returns to ?0? automatically when the initialization is finished. this initialization must be ma de after clocks are input following the pdn pin = ?l? ?h?. addr register name d23 d22 d21 d20 d19 d18 d17 d16 0fh alc volume vol7 vol6 vol5 vol4 vol3 vol2 vol1 vol0 r/w r r r r r r r r default - - - - - - - - vol7-0: current alc volume value, read operation only ( table 34 ) (alc registers) addr register name d23 d22 d21 d20 d19 d18 d17 d16 20h lch intput volume control ivl7 iv l6 ivl5 ivl4 ivl3 ivl2 ivl1 ivl0 21h rch intput volume control ivr7 iv r6 ivr5 ivr4 ivr3 ivr2 ivr1 ivr0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 1 1 1 0 0 0 0 1 ivl7-0, ivr7-0: input digital volume default: ?e1h? (+30db) addr register name d23 d22 d21 d20 d19 d18 d17 d16 22h lch output volume control ovl7 ovl6 ovl5 ovl4 ovl3 ovl2 ovl1 ovl0 23h rch output volume control ovr7 ovr6 ovr5 ovr4 ovr3 ovr2 ovr1 ovr0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 1 0 0 1 0 0 0 1 ovl7-0, ovr7-0: output digital volume default: ?91h? (0db)
[AK4950] ms1320-e-00 2011/10 - 83 - addr register name d23 d22 d21 d20 d19 d18 d17 d16 24h alc mode control 1 iref7 iref6 i ref5 iref4 iref3 iref2 iref1 iref0 25h alc mode control 2 oref7 oref6 oref5 oref4 oref3 oref2 oref1 oref0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 1 1 1 0 0 0 0 1 iref7-0: reference value of alc recovery operation (recording). 0.375db step, 242 level ( table 31 ) oref7-0: reference value of alc recovery operation (playback). 0.375db step, 242 level ( table 32 ) default: ?e1h? (+30.0db) addr register name d23 d22 d21 d20 d19 d18 d17 d16 26h alc mode control 3 0 0 wtm1 wtm0 0 0 rfst1 rfst0 r/w r r r/w r/w r r r/w r/w default 0 0 0 0 0 0 0 0 rfst1-0: alc first recovery speed ( table 33 ) default: ?00? * writing to these registers is valid only when pmfil bit =?0?. when pmfil bit = ?1?, writings are ignored. wtm1-0: alc recovery waiting period ( table 29 ) default: ?00? addr register name d23 d22 d21 d20 d19 d18 d17 d16 27h alc mode control 3 smute alc rgain2 rgain1 rgain0 0 lmth1 lmth0 r/w r/w r/w r/w r/ w r/w r r/w r/w default 0 0 0 0 0 0 0 0 lmth1-0: alc limiter detection level / recovery counter reset level ( table 27 ) default: ?00? rgain2-0: alc recovery gain step ( table 30 ) default: ?000? * writing to these registers is valid only when pmfil bit =?0?. when pmfil bit = ?1?, writings are ignored. alc: alc enable 0: alc disable (default) 1: alc enable smute: soft mute control 0: normal operation (default) 1: dac outputs soft-muted * this bit is invalid during an alc operation.
[AK4950] ms1320-e-00 2011/10 - 84 - addr register name d23 d22 d21 d20 d19 d18 d17 d16 2ah digital volume control dvol 7 dvol6 dvol5 dvol4 dvol 3 dvol2 dvol1 dvol0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 1 1 0 0 0 0 0 1 dvol7-0: output digital volume 2 ( table 39 ) default: ?c1h? (0db) addr register name d23 d22 d21 d20 d19 d18 d17 d16 2bh mic gain control 2 msgainr3 msgai nr2 msgainr1 msgainr0 m sgainl3 msgainl2 msgainl1 msgainl0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 msgainl0-3: lch mic sensitivity compensation ( table 22 ) msgainr0-3: rch mic sensitivity compensation ( table 22 ) addr register name d23 d22 d21 d20 d19 d18 d17 d16 2ch digital filter control 1 0 0 0 pfsdo pfdac adcpf ovolc ivolc r/w r r r r/w r/ w r/w r/w r/w default 0 0 0 0 0 1 1 1 ivolc: ivol control 0: independent 1: dependent (default) when ivolc bit = ?1?, ivl7-0 bits control both lch and rch volume levels, while register values of ivl7-0 bits are not written to ivr7-0 bits. ovolc: output digital volu me control mode select 0: independent 1: dependent (default) when ovolc bit = ?1?, ovl7-0 bits control both lch and rch volume levels, while register values of ovl7-0 bits are not written to ovr7-0 bits. adcpf: programmable filter / alc input signal select 0: sdti 1: alc output (default) pfdac: dac input signal select 0: sdti (default) 1: programmable filter / alc output pfsdo: sdto output signal select 0: adc (+ 1st hpf) output 1: programmable filter / alc output (default)
[AK4950] ms1320-e-00 2011/10 - 85 - addr register name d23 d22 d21 d20 d19 d18 d17 d16 2dh digital filter control 2 0 0 lpf hpf eq0 gn1 gn0 fil3 r/w r r r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 fil3: stereo emphasis filter control 0: off (default) 1: on when fil3 bit = ?1?, the settings of 8fh ~ 93h are enabled. gn1-0: gain block gain setting ( table 26) default: ?00? (0db) eq0: gain compensation filter (eq0) control 0: off (default) 1: on when eq0 bit = ?1?, the settings of 99h ~ 9dh are enabled. when eq0 bit = ?0?, eq0 block is through (0db). hpf: hpf2 coefficient setting enable 0: off (default) 1: on when hpf bit is ?1?, the settings of 83h ~ 87h are enabled. when hpf bit is ?0?, hpf2 block is through (0db). lpf: lpf coefficient setting enable 0: off (default) 1: on when lpf bit is ?1?, the settings of 89h ~ 8dh are enabled. when lpf bit is ?0?, lpf block is through (0db).
[AK4950] ms1320-e-00 2011/10 - 86 - addr register name d23 d22 d21 d20 d19 d18 d17 d16 2eh digital filter control 3 0 0 0 0 eq4 eq3 eq2 0 r/w r r r r r/w r/w r/w r default 0 0 0 0 0 0 0 0 eq2: equalizer 2 coefficient setting enable 0: disable (default) 1: enable when eq2 bit is ?1?, the settings of a0h ~ a6h are enabled. when eq2 bit is ?0?, eq2 block is through (0db). eq3: equalizer 3 coefficient setting enable 0: disable (default) 1: enable when eq3 bit is ?1?, the settings of a9h ~ afh are enabled. when eq3 bit is ?0?, eq3 block is through (0db). eq4: equalizer 4 coefficient setting enable 0: disable (default) 1: enable when eq4 bit is ?1?, the settings of b2 ~ b6h are enabled. when eq4 bit is ?0?, eq4 block is through (0db).
[AK4950] ms1320-e-00 2011/10 - 87 - register map 2 mic sensitivity compensation coefficient d23 ~ d20 d19 ~ d16 d15 ~ d12 d11 ~ d8 d7 ~ d4 d3 ~ d0 addr register name default 01h (3-wire) 81h (i 2 c) lch input volume 0001 0000 0000 0000 0000 0000 02h (3-wire) 82h (i 2 c) rch input volume 0001 0000 0000 0000 0000 0000 r/w w w w w w w * mic sensitivity compensation gain can be written to the dsp directly without setting re gister 2bh. hpf2 coefficient d23 ~ d20 d19 ~ d16 d15 ~ d12 d11 ~ d8 d7 ~ d4 d3 ~ d0 addr register name default 03h (3-wire) 83h (i 2 c) hpf a0 0001 0000 0000 0000 0000 0000 04h (3-wire) 84h (i 2 c) hpf a1 0000 0000 0000 0000 0000 0000 06h (3-wire) 86h (i 2 c) hpf b1 0000 0000 0000 0000 0000 0000 r/w w w w w w w * when the coefficients are in default setting, audio data pa sses through this block by 0db gain even if hpf bit = ?1?. lpf coefficient d23 ~ d20 d19 ~ d16 d15 ~ d12 d11 ~ d8 d7 ~ d4 d3 ~ d0 addr register name default 09h (3-wire) 89h (i 2 c) lpf a0 0001 0000 0000 0000 0000 0000 0ah (3-wire) 8ah (i 2 c) lpf a1 0000 0000 0000 0000 0000 0000 0ch (3-wire) 8ch (i 2 c) lpf b1 0000 0000 0000 0000 0000 0000 r/w w w w w w w * when the coefficients are in default setting, audio data pa sses through this block by 0db gain even if lpf bit = ?1?. stereo emphasis fil3 coefficient d23 ~ d20 d19 ~ d16 d15 ~ d12 d11 ~ d8 d7 ~ d4 d3 ~ d0 addr register name default 0fh (3-wire) 8fh (i 2 c) stereo filter a0 0001 0000 0000 0000 0000 0000 10h (3-wire) 90h (i 2 c) stereo filter a1 0000 0000 0000 0000 0000 0000 11h (3-wire) 91h (i 2 c) stereo filter a2 0000 0000 0000 0000 0000 0000 12h (3-wire) 92h (i 2 c) stereo filter b1 0000 0000 0000 0000 0000 0000 13h (3-wire) 93h (i 2 c) stereo filter b2 0000 0000 0000 0000 0000 0000 r/w w w w w w w * when the coefficients are in default setting, audio data pa sses through this block by 0db gain even if fil3 bit = ?1?.
[AK4950] ms1320-e-00 2011/10 - 88 - stereo emphasis eq0 (gain compensation) coefficient d23 ~ d20 d19 ~ d16 d15 ~ d12 d11 ~ d8 d7 ~ d4 d3 ~ d0 addr register name default 19h (3-wire) 99h (i 2 c) eq0 a0 0001 0000 0000 0000 0000 0000 1ah (3-wire) 9ah (i 2 c) eq0 a1 0000 0000 0000 0000 0000 0000 1bh (3-wire) 9bh (i 2 c) eq0 a2 0000 0000 0000 0000 0000 0000 1ch (3-wire) 9ch (i 2 c) eq0 b1 0000 0000 0000 0000 0000 0000 1dh (3-wire) 9dh (i 2 c) eq0 b2 0000 0000 0000 0000 0000 0000 r/w w w w w w w * when the coefficients are in default setting, audio data pa sses through this block by 0db gain even if eq0 bit = ?1?. eq2 coefficient d23 ~ d20 d19 ~ d16 d15 ~ d12 d11 ~ d8 d7 ~ d4 d3 ~ d0 addr register name default 20h (3-wire) a0h (i 2 c) eq2 a0 0001 0000 0000 0000 0000 0000 21h (3-wire) a1h (i 2 c) eq2 a1 0000 0000 0000 0000 0000 0000 22h (3-wire) a2h (i 2 c) eq2 a2 0000 0000 0000 0000 0000 0000 23h (3-wire) a3h (i 2 c) eq2 b1 0000 0000 0000 0000 0000 0000 24h (3-wire) a4h (i 2 c) eq2 b2 0000 0000 0000 0000 0000 0000 25h (3-wire) a5h (i 2 c) eq2 b1 0000 0000 0000 0000 0000 0000 26h (3-wire) a6h (i 2 c) eq2 b2 0000 0000 0000 0000 0000 0000 r/w w w w w w w * when the coefficients are in default setting, audio data pa sses through this block by 0db gain even if eq2 bit = ?1?. eq3 coefficient d23 ~ d20 d19 ~ d16 d15 ~ d12 d11 ~ d8 d7 ~ d4 d3 ~ d0 addr register name default 29h (3-wire) a9h (i 2 c) eq3 a0 0001 0000 0000 0000 0000 0000 2ah (3-wire) aah (i 2 c) eq3 a1 0000 0000 0000 0000 0000 0000 2bh (3-wire) abh (i 2 c) eq3 a2 0000 0000 0000 0000 0000 0000 2ch (3-wire) ach (i 2 c) eq3 b1 0000 0000 0000 0000 0000 0000 2dh (3-wire) adh (i 2 c) eq3 b2 0000 0000 0000 0000 0000 0000 2eh (3-wire) aeh (i 2 c) eq3 b1 0000 0000 0000 0000 0000 0000 2fh (3-wire) afh (i 2 c) eq3 b2 0000 0000 0000 0000 0000 0000 r/w w w w w w w * when the coefficients are in default setting, audio data passes through this block by 0db gain even if eq3 bit = ?1?. eq4 coefficient
[AK4950] ms1320-e-00 2011/10 - 89 - d23 ~ d20 d19 ~ d16 d15 ~ d12 d11 ~ d8 d7 ~ d4 d3 ~ d0 addr register name default 32h (3-wire) b2h (i 2 c) eq4 a0 0001 0000 0000 0000 0000 0000 33h (3-wire) b3h (i 2 c) eq4 a1 0000 0000 0000 0000 0000 0000 34h (3-wire) b4h (i 2 c) eq4 a2 0000 0000 0000 0000 0000 0000 35h (3-wire) b5h (i 2 c) eq4 b1 0000 0000 0000 0000 0000 0000 36h (3-wire) b6h (i 2 c) eq4 b2 0000 0000 0000 0000 0000 0000 r/w w w w w w w * when the coefficients are in default setting, audio data passes through this block by 0db gain even if eq4 bit = ?1?. eq1 coefficient d23 ~ d20 d19 ~ d16 d15 ~ d12 d11 ~ d8 d7 ~ d4 d3 ~ d0 addr register name default 6bh (3-wire) ebh (i 2 c) eq1a0 0001 0000 0000 0000 0000 0000 6ch (3-wire) ech (i 2 c) eq1 a1 0000 0000 0000 0000 0000 0000 6dh (3-wire) edh (i 2 c) eq1 a2 0000 0000 0000 0000 0000 0000 6eh (3-wire) eeh (i 2 c) eq1 b1 0000 0000 0000 0000 0000 0000 6fh (3-wire) efh (i 2 c) eq1 b2 0000 0000 0000 0000 0000 0000 r/w w w w w w w * when the coefficients are in default setting, audio data passes through this block by 0db gain even if eq1 bit = ?1?.
[AK4950] ms1320-e-00 2011/10 - 90 - system design figure 65 shows the system connection diagram. an evaluation boa rd (akd4950) is available for fast evaluation as well as suggestions for peripheral circuitry. power supply 2.7 3.6v 0.1u dsp p speaker 10u analog ground digital ground 1u 1u 20k 20k 200 200 vss3 a vdd vcom vss1 vout vss4 pvee vin spn spp i2c regfil a regfilb mcko mcki vss2 rout lout lin1 rin1 mpwr lin2 rin2 pdn tvdd bick lrck sdto sdti cdtio cclk csn AK4950 top view 25 26 27 28 29 30 31 32 24 23 22 1 16 15 14 13 12 11 10 9 21 20 19 18 17 2 3 4 5 6 7 8 2.2u 1.0u 0.1u 0.1u 2.2u 0.1u 2.2k 2.2k 2.2k 2.2k video out 0.1u 0.1u 2.2u video in 75 line out internal mic external mic power supply 1.6 3.6v notes: - vss1, vss2, vss3 and vss4 of the AK4950 must be distributed separately from the ground of external controllers. - all digital input pins must not be allowed to float. - when the AK4950 is used in master mode, lrck and bick pins are floating before m/s bit is changed to ?1?. therefore, around 100k pull-up resistor must be connected to lrck and bick pins of the AK4950. figure 65. system connection diagram (3-wire mode, stereo lineout pmbp bit = ?0?)
[AK4950] ms1320-e-00 2011/10 - 91 - 1. grounding and power supply decoupling the AK4950 requires careful attention to power supply and grounding arrangements. a ceramic capacitor of 0.1 f or more should be connected to between avdd and vss1/3/4 . if avdd and tvdd are supplied separately, the power-up sequence is not critical. vss1, vss2, vss3 and vss4 of the AK4950 must be connected to the analog ground plane. system analog ground and digital ground should be wired separately and connected together as close as possible to where the supplies are brought onto the printed circuit board. decoupling capacitors must be as near to the AK4950 as possible, with the small value ceramic capacitor being the nearest. 2. internal regulated voltage power supply vcom is a signal ground of this chip. a 2.2 f electrolytic capacitor in parallel with a 0.1 f ceramic capacitor attached to the vcom pin eliminates the effects of high frequency noise. no load current may be drawn from the vcom pin. all signals, especially clocks, should be kept away from the vcom pin in order to avoid unwanted coupling into the AK4950. 3. analog inputs the mic and line inputs supports single-ended. the input signa l range scales with nominally at typ. 0.9 x 2.3vpp (@ mgain = 0db), centered around the internal signal ground (typ. 1.15v). usually the input signal is ac coupled with a capacitor. the cut-off frequency is fc = 1/(2 rc). the AK4950 can accept input voltages from vss1 to avdd. 6. analog outputs the input data format for the dac is 2?s complement. th e output voltage is a positive full scale for 7fffffh (@24bit) and a negative full scale for 800000h (@24bit). the ideal output is vcom voltage for 000000h (@24bit data). the common voltage of stereo lineout is 1.35v or 1.43v (typ) and the speaker output is centered on avdd/2 (typ).
[AK4950] ms1320-e-00 2011/10 - 92 - control sequence clock set up when adc, dac, digital microphone a nd programmable filter are used, the clocks must be supplied. 1. pll master mode bick pin lrck pin mcko bit (addr:01h, d17) pmpll bit (addr:01h, d16) 10msec(max) output (1) (7) power supply pdn pin mcki pin (3) (2) input m/s bit (addr:01h, d3) mcko pin output (9) (8) 10msec(max) 1msec(min) pll3-0 bits (addr:07h, d20-23) fs3-0 bits (addr:08h, d19-16) default default "1011" (4) (5) (6) "1100" 10msec(max) init bit (addr:0eh, d16) (10) example: audio i/f format: msb justified (adc & dac) bick frequency at master mode: 64fs input master clock select at pll mode: 13.5mhz mcko: enable sampling frequency: 48khz (1) power supply & pdn pin = ?l? ? ?h? (3) addr:01h, data:0ah mcko, bick and lrck output (4 ) addr:07h, data:c2h ( 5 ) addr:08h, data:0bh (6) addr:01h, data:0bh (2) wait time (min)1ms figure 66. clock set up sequence (1) (1) after power up, pdn pin = ?l? : ?h? ?l? time (1) of 150ns or more is needed to reset the AK4950. (2) pdn pin reset release waiting time wait time of 1ms or more is needed for the internal vcom voltage rising. (3) in case of using mcko output: mcko bit = ?1? in case of not using mcko output: mcko bit = ?0? (4) pll mode setting. (when the reference cloc k is mcki = 13.5mhz, pll3-0 bits = ?1100?) (5) sampling frequency setting. (in case of fs = 48khz, fs3-0 bits = ?1011?) (6) pll lock time is 10ms (max) after pmpll bit changes from ?0? to ?1? and mcki is supplied from an external source. (7) the AK4950 starts outputting the lrck and bick cl ocks after the pll becomes stable and the normal operation starts. (8) invalid clock is output from mcko pin during this period when mcko bit = ?1?. (9) normal clock is output from the mcko pin af ter pll is locked when mcko bit = ?1?. (10) digital function initializing digital functions can be initialized by setting init bit = ?0? : ?1? after normal clock is output from the mcko pin. the initializing time is 1/512fs x 18,000 [s]. init bit returns to ?0? automatically when the initialization is finished. this initialization must be executed when using alc and programmable filter.
[AK4950] ms1320-e-00 2011/10 - 93 - 2. when the external clock (bick pi n) is used in pll slave mode. pmpll bit (addr:01h, d16) (1) (6) power supply pdn pin bick pin lrck pin (2) input internal clock 1msec(min) pll3-0 bits (addr:07h, d20-23) fs3-0 bits (addr:08h, d19-16) default "0011" default "10xx" (3) (4) (5) init bit (addr:0eh, d16) (7) 4fs of example: audio i/f format : msb justified (adc & dac) pll reference clock: bick bick frequency: 64fs sampling freque ncy: 48khz (1) power supply & pdn pin = ?l? ? ?h? ( 4 ) addr:08h, data:08h (3) addr:07h, data:32h ( 5 ) addr:01h, data:01h (2) wait time (min)1ms figure 67. clock set up sequence (2) (1) after power up: pdn pin ?l? ?h? ?l? time (1) of 150ns or more is needed to reset the AK4950. (2) pdn pin reset release waiting time wait time of 1ms or more is needed for the internal vcom voltage rising. (3) pll mode setting. (when the reference clock is bick = 64fs, pll3-0 bits = ?0011?) (4) sampling frequency setting. (in case of fs = 48khz, fs3-0 bits = ?10xx?) (5) pll lock time is 2ms (max) after the pmpll bit cha nges from ?0? to ?1? and pll reference clock (bick pin) is supplied. (6) normal operation starts after the pll is locked. (7) digital function initializing digital functions can be initialized by setting init bit = ?0? ?1? after normal clock is output. the initializing time is 1/512fs x 18,000 [s]. init bit returns to ?0? au tomatically when the initiali zation is finished. this initialization must be executed when using alc and programmable filter.
[AK4950] ms1320-e-00 2011/10 - 94 - 3. when the external clock (mcki pi n) is used in pll slave mode. bick pin lrck pin mcko bit (addr:01h, d17) pmpll bit (addr:01h, d16) input (1) (9) power supply pdn pin mcki pin (3) (2) input mcko pin output (7) (8) 10msec(max) 1msec(min) pll3-0 bits (addr:07h, d20-23) fs3-0 bits (addr:08h, d19-16) default default "1011" (4) (5) (6) "1100" init bit (addr:0eh, d16) (10) 10msec(max) example: audio i/f format: msb justified (adc & dac) bick frequency at slave mode : 64fs input master clock select at pll mode: 13.5mhz m cko: en able sampling frequency: 48kh z (1) p ower suppl y & pdn pi n = ?l? ? ?h? (3) addr:01h, data:02h bick and lrck input start (4 ) addr:07h, data:c2h (5) addr:08h, data:0bh (6) addr:01h, data:03h (2) wait time (min)1ms mcko output start figure 68. clock set up sequence (3) (1) after power up: pdn pin ?l? ?h? ?l? time (1) of 150ns or more is needed to reset the AK4950. (2) pdn pin reset release waiting time wait time of 1ms or more is needed for the internal vcom voltage rising. (3) in case of using mcko output: mcko bit = ?1? in case of not using mcko output: mcko bit = ?0? (4) pll mode setting. (when the reference cloc k is mcki = 13.5mhz, pll3-0 bits = ?1100?) (5) sampling frequency setting. (in case of fs = 48khz, fs3-0 bits = ?1011?) (6) pll lock time is 10ms (max) after the pmpll bit cha nges from ?0? to ?1? and pll reference clock (mcki pin) is supplied. (7) normal clock is output from the mcko pin after pll is locked. (8) invalid clock is output from mcko pin during this period. (9) bick and lrck clocks should be synchronized with mcko clock. (10) digital function initializing digital functions can be initialized by setting init bit = ?0? ?1? after normal clock is output. the initializing time is 1/512fs x 18,000 [s]. init bit returns to ?0? au tomatically when the initiali zation is finished. this initialization must be executed when using alc and programmable filter.
[AK4950] ms1320-e-00 2011/10 - 95 - 4. ext slave mode (1) power supply pdn pin fs3-0 bits (addr:08h, d19-16) (2) (3) lrck pin bick pin (4) input (4) mcki pin input init bit (addr:0eh, d16) (5) example: audio i/f format: msb justified (adc and dac) input mcki frequency: 512fs mcko: disable (1) power supply & pdn pin = ?l? ? ?h? ( 3 ) addr:08h, data:03h mcki, bick and lrck input (2) wait time (min)1ms figure 69. clock set up sequence (4) (1) after power up: pdn pin ?l? ?h? ?l? time (1) of 150ns or more is needed to reset the AK4950. (2) pdn pin reset release waiting time wait time of 1ms or more is needed for the internal vcom voltage rising. (3) sampling frequency setting. (in case of fs = 48khz, fs3-0 bits = ?xx11?) (4) normal operation starts after the mcki, lrck and bick are supplied. (5) digital function initializing digital functions can be initialized by setting init bit = ?0? ?1? after normal clock is supplied. the initializing time is 1/512fs x 18,000 [s]. init bit returns to ?0? automatically when th e initialization is finished. this initialization must be executed when using alc and programmable filter.
[AK4950] ms1320-e-00 2011/10 - 96 - mic input recording (stereo) example: control i/f = 3-wire pll master mode (mcko output) audio i/f format: msb justified pre mic amp: +18db mic power on sampling frequency: 48khz alc setting:refer to table 34 hpf2: fc=150hz, adrst bit = ?0? ( 3 ) addr:20h, data:e1h ( 1 ) addr:01h, data:0fh ( 4 ) addr:24h, data:e1h ( 5 ) addr:26h, data:30h ( 6 ) addr:27h, data:59h ( 7 ) addr:2ch, data:17h (8) addr:26h, data:03h (9) addr:0dh, data:01h (10) addr:03h, data:0fd82dh addr:04h, data:fd27d4h a ddr:06h , data:0fb05bh ( 11 ) addr:00h , data:83h recordin g (2) addr:02h, data:06h ( 12 ) addr:00h, data:00h ( 13 ) addr:27h, data:19h figure 70. mic input recording sequence this sequence is an example of alc1 setting at fs=48khz. if the parameter of the alc1 is changed, please refer to the figure 39 . at first, clocks shoul d be supplied according to ? clock set up ? sequence. (1) power up mic power: pmmp bit = ?0? ?1?, adrst bit (initializing cycle) setting (addr = 01h) (2) set up gain for microphone by mgain3-0 bits (addr = 02h) (3) set up alc starting ivol value. (addr = 20h) (4) set up iref value. (addr = 24h) (5) set up rfst1-0 and wtm1-0 bits for alc (addr= 26h) (6) set up lmth1-0, rgain2-0 bits and alc bit. (addr=27h) (7) set up programmable filter path: pfs do bit = adcpf bit = ?1? (addr=2ch) (8) switch on/off of the programmable filter: hpf bit = ?1? (addr= 2dh) (9) set up coew bit = ?1? (addr = 0dh) when coew bit = ?1?, registers on the register map 1 and 2 can be accessed. set the most significant bit (msb) of the control data to ?1? ( figure 52 ) to access registers on the register map 1, and set ?0? to access registers on the register map 2 ( figure 53 ). (10) set up coefficient of the programmable filter (addr=03h, 04h, 06h: control data mdb = ?l?) (11) power up of the adc and programmable filter: (pmadl=pmadr=pmpfil bits = ?0? : ?1?) the initialization cycle of the adc is 1059/fs=22.06ms@fs=48khz when adrst bit = ?0?. adc outputs ?0? during the initialization. alc starts operation at the value set by ivol (3). (12) power down of the microphone, adc and progra mmable filter: (pmadl=pmadr=pmpfil bits = ?1? : ?0?) (13) alc disable: alc bit ?1? : ?0? pmpfil bit pmadl/r bit (addr:00h, d16, d17, d23 control data msb = 'h') sdto pin state 0fh xxh x, xxx 0 data output normal data output (11) alc state alc enable alc disable (6) xxh 17h (4) alc control 1 (addr:24h ) xxh 30h alc control 2 (addr:26h) xxh e1h (5) coew bit (addr:0dh, d16) 10h (8) 0 data output (12) alc disable initialize 1059/fs (2) ivl7-0 bits (addr:20h) 0110 (3) alc control 3 (addr:27h) xxh 59h (7) xxh (1) filter co-ef (addr:03h,04h,06h control data msb = 'l') 1 (9) 0 mic control (addr:02h, d19-16) xxh e1h digital filter path (addr:2ch) filter select1 (addr:2dh) (10) xxh 0fd82dh (addr: 03h) fd27d4h (addr : 04h) 0fb05bh (addr : 06h) pmmp bit adrst bit (addr:01h, d18, d23) 19h (13)
[AK4950] ms1320-e-00 2011/10 - 97 - digital mic input (stereo) example: control i/f = 3-wire pll master mode (mcko output) audio i/f format: msb justified sam pling frequency: 48khz digital mic setting: data is latched on the dmclk failing edge alc setting:refer to table 34 hpf2: fc=150hz, adrst bit = ?0? ( 3 ) addr:24h, data:e1h ( 1 ) addr:01h, data:0bh ( 4 ) addr:26h, data:30h ( 5 ) addr:27h, data:59h ( 6 ) addr:2ch, data:17h ( 7 ) addr:2ch, data:17h (8) addr:0dh, data:01h (9) addr:03h, data:0fd82dh addr:04h, data:fd27d4h a ddr:06h , data:0fb05bh ( 11 ) addr:09h , data:37h recordin g (2) addr:20h, data:e1h ( 12 ) addr:09h, data:07h ( 13 ) addr:00h, data:00h ( 10 ) addr:00h, data:80h ( 14 ) addr:27h , data:19h figure 71. digital mic input recording sequence this sequence is an example of alc1 setting at fs=48khz. if the parameter of the alc1 is changed, please refer to the figure 39 . at first, clocks shoul d be supplied according to ? clock set up ? sequence. (1) set up adrst bit (initializing cycle) setting (addr = 01h) (2) set up alc starting ivol value. (addr = 20h) (3) set up iref value. (addr = 24h) (4) set up rfst1-0 and wtm1-0 bits for alc (addr= 26h) (5) set up lmth1-0, rgain2-0 bits and alc bit. (addr=27h) (6) set up programmable filter path: pfsdo bit = adcpf bit = ?1? (addr=2ch) (7) switch on/off of the programmable filter: hpf bit = ?1? (addr= 2dh) (8) set up coew bit = ?1? (addr = 0dh) when coew bit = ?1?, registers on the register map 1 and 2 can be accessed. set the most significant bit (msb) of the control data to ?1? ( figure 52 ) to access registers on the register map 1, and set ?0? to access registers on the register map 2 ( figure 53 ). (9) set up coefficient of the programmable filter (addr=03h, 04h, 06h: control data msb = ?l?) (10) power up of the programmable filter: (pmadl=pmadr=pmpfil bits = ?0? ?1?) (11) power up and set the digital mic: (pmdmr=pmdml bits = ?0? ?1?) the initialization cycle of the adc is 1059/fs=22.06ms@fs=48khz when adrst bit = ?0?. adc outputs ?0? during the initialization. alc starts operation at the value set by ivol (4). (12) power-down the digital mic. pmdmr=pmdml bits ?1? ?0? (13) programmable filter power-down alc disable: pmpfil bit ?1? ?0? (14) alc1 disable: alc1 bit = ?1? ?0? pmpfil bi (addr:00h, d23 control data msb = 'h') sdto pin state 1 x 0 data output normal data output (10) alc state alc enable alc disable (5) xxh 17h (3) alc control 1 (addr:24h ) xxh 30h alc control 2 (addr:26h) xxh e1h (4) coew bit (addr:0dh, d16) 10h (7) 0 data output (11) alc disable 1059/fs ivl7-0 bits (addr:20h) (2) alc control 3 (addr:27h) xxh 59h (6) xxh (1) filter co-ef (addr:03h,04h,06h control data msb = 'l') 1 (8) 0 xxh e1h digital filter path (addr:2ch) filter select1 (addr:2dh) (9) xxh 0fd82dh (addr: 03h) fd27d4h (addr : 04h) 0fb05bh (addr : 06h) adrst bit (addr:01h, d23) 19h (14) 00h digital mic (addr:09h) 37h 07h (12) (13)
[AK4950] ms1320-e-00 2011/10 - 98 - speaker-amp output alc control 3 (addr:27h) pmpfil bit pmdac bit (addr:00h, d23, d18) pmspk bit (addr:00h, d20) xxh 59h spp pin normal output sppsn bit dacs bit (addr:04h, d23, d17) hi-z hi-z spn pin normal output hi-z hi-z avdd/2 avdd/2 (6) 30h xxh (4) alc control 2 (addr:26h) (7) (8) (10) (9) 01 xx (1) spkg1-0 bits (addr:03h, d21-20) (3) ovl7-0 bits (addr:22h) xxh 91h (2) alc control 1 (addr:25h) xxh a1h digital filter path (addr:2ch) xxh 08h (5) alc enable alc disable alc state alc disable example: pll master mode audio i/f format: msb justified sampling frequency:48khz digital volume: 0db alc: enable, oref : +6db programmable filter off (2) addr:22h, data:91h (6) addr:2ch, data:08h ( 1 ) addr:03h, data:10h (7) addr:00h, data:94h ( 9 ) addr:04h, data:00h ( 10 ) addr:00h, data:00h pla y back (3) addr:25h, data:a1h (4) addr:26h, data:30h (5) addr:27h, data:59h ( 8 ) addr:04h, data:82h figure 72. speaker-amp output sequence at first, clocks should be supplied according to ?clock set up? sequence. (1) set up spk-amp gain: spkg1-0 bits = ?00? ?01? (addr = 03h) (2) set up ovol value for output digital volume. (addr = 22h) this is the alc stating ovol value. when ovolc b it = ?1?, ovl7-0 bits (addr= 22h) controls lch and rch volumes. after the digital block is powered-up, th e volume changes to the set value set from the default value (0db) in soft transition. when alc bit is ?0?, this volume can be used as a digital volume. (3) set up oref value. (addr = 25h) (4) set up rfst1-0 bits and wtm1-0 bits. (addr= 26h) (5) set up lmth-0 bits, rgain2-0 bits and alc bit. (addr=27h) (6) set up programmable filter path: pesdo = adcpf = pfdac bits = ?1? (addr = 2ch) (7) power up dac, programmable filter and speaker-amp: pmpfil = pmspk = pmdac bits = ?0? ?1? (8) exit power-save mode of speaker-amp: sppsn bit = ?1? ?0? dac spk-amp path setting: dacs bit = ?0? ?1? (9) enter speaker-amp power save mode: sppsn bit = ?0? ?1? disables dac spk-amp path: dacs bit = ?1? ?0? (10) power down dac, min-amp, programmable filter and speaker-amp. pmpfil = pmspk = pmdac bits = ?1? ?0?
[AK4950] ms1320-e-00 2011/10 - 99 - stereo line output dvol7-0 bits (addr:2ah) pmdac bit (addr:00h, d18) pmlo bit (addr:00h, d19) xxh c1h lout pin rout pin (3) (1) (4) normal output (6) (5) >300 ms (7) (8) >300 ms lops bit (addr:04h, d22) dacl bit (addr:04h, d16) digital filter path (addr:2ch) 17h (2) xxh example: pll, master m ode au dio i/f form at :m sb just ified sampling frequency:48khz digital volume 2: 0db program ma ble filter off (1) addr:2ah, data:c1h (2) addr:2ch, data:17h (4) addr:00h, data0c:h (5) addr:04h, data:01ch playback (6) addr:04h, data:41h (7) addr:00h, data:00h (8) addr:04h, data:00h (3) addr:04h, data:41h figure 73. stereo lineout sequence at first, clocks should be supplied according to ?clock set up? sequence. (1) set up output digital volume 2 (addr = 2ah) (2) set up programmable filter path (pfdac , adcpf and pfsdo bits). (addr = 2ch) (3) set up the path of ?dac stereo lime-amp?: dacl bit = ?0? ?1? (addr = 04h) set stereo lime amp to power save mode. lops bit = ?0? ?1? (4) power up dac and stereo line-amp: pmdac = pmlo bits = ?0? ?1? (addr = 00h) lout and rout pins rise up to vcom voltage after pm lo bit is changed to ?1?. rise time is 300ms(max.) at c=1 p f and avdd=1.8v. (5) exit power-save mode of st ereo line-amp: lops bit = ?1? ?0? (addr=04h) lops bit should be set to ?0? after lout and rout pins rise up. stereo line-amp goes to normal operation by setting lops bit to ?0?. (6) enter power save mode of stereo line-amp: lops bit = ?0? ?1? (addr = 04h) (7) power down dac and stereo line-amp: pmdac=pmlo= ?1? ?0?. (addr=00h) lout and rout pins fall down to vss1. fall time is 300ms (max.) at c=1 p f and avdd=1.8v. (8) disable the path of ?dac stereo line-amp?: dacl bit = ?1? ?0? (addr=04h) exit power-save mode of the st ereo-line amp: lops bit = ?1? o ?0? lops bit should be set to ?0? after lout and rout pins fall down.
[AK4950] ms1320-e-00 2011/10 - 100 - mono output signal from speaker pmspk bit (addr:00h, d20) beeps bit ( addr:04h, d19 ) spp pin normal output sppsn bit (addr:04h, d23) hi-z hi-z spn pin normal output hi-z hi-z a vdd/2 a vdd/2 ( 2 ) (1) (5) (4) pmbp bit (addr:00h, d21) clocks can be stopped. clock (3) (6) example: (1) addr:00h, data:30h (2) addr:04h, data: 08h mono signal output (3) addr:04h, data:d23 (4) addr:00h, data:00h (5) addr:04h, data:00h figure 74. ? min-amp ? speaker-amp ? output sequence when only the path of ?min-amp : srk-amp? is in operation, the clocks are not needed. (1) power up min-amp and speaker-amp: pmbp = pmspk bits = ?0? : ?1? (2) disable the path of ?dac : spk-amp?: dacs bit = ?0? enable the path of ?min : spk-amp?: beeps bit = ?0? : ?1? (3) exit power-save mode of spk-amp: sppsn bit = ?0? : ?1? this period should be set in accordance with the time cons tant of the capacitor (c) a nd resistor (r) connected to the min pin. pop noise may occur if the spk-amp output is enabled before the min-amp input is stabilized. e.g. r=33k , c=0.1 f: recommended waiting time is 5 2 = 16.5ms or more. (4) enter power-save mode of the spk-amp: sppsn bit = ?1? : ?0? (5) power down min-amp and spk-amp: pmbp = pmspk bits = ?1? : ?0? (6) disable the path of ?min : spk-amp?: beeps bit = ?1? : ?0?
[AK4950] ms1320-e-00 2011/10 - 101 - video input/output example: audio function :no use video gain = +6db ( 2 ) addr:0ch, data:03h video out p ut ( 3 ) addr:0ch, data:00h ( 1 ) addr:0ch, data:00h figure 75. video output sequence when only the video block is in operation, the clocks are not needed. (1) set up the video gain (vg1-0 bits). (2) power up video amp and charge pump: pmv, pmcp bits = ?0? ?1? it takes maximum 300ms to a stable operation of clamp circuit. (input capacitor at the vin pin = 1.0uf) (3) power down video amp: pmv, pmcp bits = ?0? ?1? the vout pin output is stopped and becomes 0v. (2) vout pin vss1 vss1 normal out p u t (1) vg1-0 bits (addr: 0ch, d19-18) 00 xx clocks clocks can be sto pp ed, if onl y video out p ut is enabled. pmcp bi t (addr: 0ch, d17) pmv bi t (addr: 0ch, d16) 1 1 0 0 0 0 (3) max 300ms (vin input capacitor = 1.0uf)
[AK4950] ms1320-e-00 2011/10 - 102 - stop of clock master clock can be stopped when adc, dac, digital mic and programmabl e filter are not in operation. 1. pll master mode external mcki pmpll bit (addr:01h, d16) mcko bit (addr:01h, d17) input (3) (1) (2) "0" or "1" example: audio i/f format: msb justified (adc & dac ) bick frequency at master mode: 64fs input master clock select at pll mode ( 3 ) sto p an external mcki ( 1 ) ( 2 ) addr:01h, data:08h figure 76. clock stopping sequence (1) (1) power down pll: pmpll bit = ?1? ?0? (2) stop mcko clock: mcko bit = ?1? ?0? (3) stop the external master clock. 2. pll slave mode (bick pin) external bick pmpll bit (addr:01h, d016 input (1) (2) external lrck input (2) example audio i/f format : msb justified (adc & dac) pll reference clock: bick bick frequency: 64fs (1) addr:01h, data:00h (2) stop the external clocks figure 77. clock stopping sequence (2) (1) power down of the pll: pmpll bit = ?1? ?0? (2) stop the external master clock.
[AK4950] ms1320-e-00 2011/10 - 103 - 3. pll slave mode (mcki pin) external mcki pmpll bit (addr:01h, d16) input (1) (2) mcko bit (addr:01h, d17) (1) example audio i/f format: msb justified (adc & dac) pll reference clock: mcki bick frequency: 64fs (1) addr:01h, data:00h (2) stop the external clocks figure 78. clock stopping sequence (3) (1) power down pll: pmpll bit = ?1? ?0? stop the mcko output: mcko bit = ?1? ?0? (2) stop the external master clock. 4. external clock mode external lrck input (1) external bick input (1) external mcki input (1) example audio i/f format :msb justified(adc & dac) input mcki frequency:1024fs (1) stop the external clocks figure 79. clock stopping sequence (4) (1) stop the external mcki, bick and lrck clocks. power down power supply current can be shut down (typ. 1 p a) by stopping clocks a nd setting pdn pin = ?l?. when the pdn pin = ?l?, the registers are initialized.
[AK4950] ms1320-e-00 2011/10 - 104 - package 32pin qfn (unit: mm) 2.8 0.1 0.4 0.20 0.05 2.8 0.1 1 9 16 25 4.0 0.1 4.0 0.1 0.35 0.10 a b 8 32 17 24 exposed pad 0.40 0.10 0.75 0.05 c0.35 note: the exposed pad on the bottom surface of th e package must be connected to the ground. material & lead finish package molding compound: epoxy resin, halogen (br and cl) free lead frame material: cu alloy lead frame surface treatmen t: solder (pb free) plate
[AK4950] ms1320-e-00 2011/10 - 105 - marking 4950 xxxx 1 xxxx: date code (4 digit) pin #1 indication date (yy/mm/dd) revision reason page contents 11/10/13 00 first edition revision history
[AK4950] ms1320-e-00 2011/10 - 106 - important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application exampl es of the semiconductor products. you are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your e quipments. akm assumes no responsibility fo r any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the applica tion or use of such information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility fo r such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to functi on or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products , who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above conten t and conditions, and the buyer or distributor agrees to assume any and all responsib ility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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